🤖 AI Summary
To address the data scarcity challenge in VLSI physical layout generation at advanced technology nodes, this paper proposes a few-shot template-guided diffusion-based inpainting framework. The method formulates layout synthesis as a progressive, design-rule-constrained denoising and completion process, requiring only 20 rule-compliant layouts to achieve high legality and structural diversity. Innovatively integrating fine-tuned image foundation models, template-driven inpainting, explicit design rule embedding, and post-hoc verification, it achieves, for the first time, fully legal 2D metal interconnect layout generation under complex Intel 18A (sub-3 nm) design rules. Experimental results demonstrate an 1.87× improvement in legality rate over prior approaches, significantly enhanced layout diversity, and production-readiness for industrial deployment.
📝 Abstract
Generating diverse VLSI layout patterns is essential for various downstream tasks in design for manufacturing, as design rules continually evolve during the development of new technology nodes. However, existing training-based methods for layout pattern generation rely on large datasets. In practical scenarios, especially when developing a new technology node, obtaining such extensive layout data is challenging. Consequently, training models with large datasets becomes impractical, limiting the scalability and adaptability of prior approaches. To this end, we propose PatternPaint, a diffusion-based framework capable of generating legal patterns with limited design-rule-compliant training samples. PatternPaint simplifies complex layout pattern generation into a series of inpainting processes with a template-based denoising scheme. Furthermore, we perform few-shot finetuning on a pretrained image foundation model with only 20 design-rule-compliant samples. Experimental results show that using a sub-3nm technology node (Intel 18A), our model is the only one that can generate legal patterns in complex 2D metal interconnect design rule settings among all previous works and achieves a high diversity score. Additionally, our few-shot finetuning can boost the legality rate with 1.87X improvement compared to the original pretrained model. As a result, we demonstrate a production-ready approach for layout pattern generation in developing new technology nodes.