Late Breaking Results: CHESSY: Coupled Hybrid Emulation with SystemC-FPGA Synchronization

2026-04-11

AI Summary

This work addresses the limitations of existing hybrid simulation tools, which often rely on vendor-specific FPGA solutions and lack open-source support, thereby hindering early validation of complex cyber-physical systems requiring efficient and precise timing modeling. The paper presents the first open-source, vendor-agnostic SystemC-FPGA tightly coupled co-simulation framework, seamlessly integrating FPGA hardware acceleration with a SystemC virtual platform via a JTAG interface. A custom synchronization wrapper is introduced to enable cycle-accurate coordination between software and hardware components. Demonstrated on a RISC-V SoC for biosignal processing, the framework achieves a 2,500× speedup over RTL simulation while keeping total simulation time within twice that of pure FPGA-based simulation, effectively balancing speed, timing accuracy, and portability at the full-system level.

Technology Category

• Cognitive Modeling & Cognitive Systems: Simulating Human Behavior
• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• User Modeling, Personalization and Recommendation: User modeling and simulation for interactive and conversational systems
• Security and Privacy: Large-scale security measurements

Abstract

The growing complexity of cyber-physical systems (CPSs) calls for early prototyping tools that combine accuracy, speed, and usability. Virtual Platforms (VPs) provide fast functional simulation, but hybrid co-emulation solutions, in which key digital components are deployed on FPGA, become necessary when accurate timing modelling is required and RTL simulation is too costly. However, existing hybrid emulation tools are mostly proprietary, and rely on vendor-specific FPGA features. To address this gap, we introduce an open-source framework that connects SystemC-based VPs with FPGA emulation, enabling full-system co-emulation of digital and non-digital components. The FPGA accelerates the execution of main digital subsystems, while a wrapper coordinates timing and communication with the VP through JTAG, maintaining synchronization with simulated peripherals. Evaluations using a RISC-V SoC, with an example in the biosignals processing domain, show up to 2500x speedup compared to RTL simulation, while maintaining less than 2x total simulation time relative to pure FPGA emulation.

Problem

• hybrid emulation
• cyber-physical systems
• SystemC
• FPGA
• virtual platforms

Innovation

• hybrid co-emulation
• SystemC-FPGA synchronization
• open-source framework
• cyber-physical systems
• virtual platform