Memory Wall is not gone: A Critical Outlook on Memory Architecture in Digital Neuromorphic Computing

2025-07-06

IEEE Computer Society Annual Symposium on VLSI

AI Summary

Although digital neuromorphic computing adopts near-memory architectures, on-chip memory systems still impose a significant memory wall that limits energy and area efficiency, hindering deployment in edge scenarios. This work challenges the prevailing notion that the memory wall has been resolved by demonstrating, for the first time, that on-chip memories such as SRAM and STT-MRAM themselves constitute primary bottlenecks for performance and energy efficiency. By developing energy and area models for various memory technologies and integrating them into representative digital neuromorphic architectures, the study quantifies the overheads of different memory solutions, revealing that current designs fall short of edge application requirements. The analysis further identifies critical directions for future memory architecture re-design to overcome these limitations.

Technology Category

• Machine Learning: Learning on the Edge & Model Compression
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Humans and AI: Other Foundations of Human Computation & AI

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs

Abstract

The rapid advancement of neuromorphic technology aims to address the memory wall challenge inherent in conventional von Neumann architectures. This paper critically examines current digital neuromorphic processors and their strategies to mitigate this bottleneck. While designed to bring computation closer to memory through distributed architectures, our findings indicate that on-chip memory systems, including SRAM and emerging technologies like STT-MRAM, have become significant consumers of area and energy, leading to a new memory wall. Through an analysis of energy and area efficiency in various memory technologies, we argue that without a re-evaluation of memory organization, digital neuromorphic processors may struggle to compete effectively in edge and embedded applications. We conclude with potential pathways for future research to overcome the limitations of on-chip memory in neuromorphic systems.

Problem

• Memory Wall
• Neuromorphic Computing
• On-chip Memory
• Energy Efficiency
• Area Efficiency

Innovation

• memory wall
• neuromorphic computing
• on-chip memory
• energy efficiency
• STT-MRAM