qPRO-AQFP: Post-Routing Optimization of AQFP Circuits with Delay Line Clocking

2026-04-09

AI Summary

This work addresses the high buffer overhead and timing convergence challenges in conventional Adiabatic Quantum-Flux-Parametron (AQFP) circuits, which stem from stringent gate-level clocking constraints and limited interconnect lengths. The authors propose a frequency-aware post-routing optimization framework that jointly optimizes clock period, path delay, and timing slack under a delay-line clocking architecture. For the first time, the frequency dependence of AQFP setup and hold times is explicitly modeled within the optimization process, enabling user-defined multi-objective trade-offs. The method also automates phase skipping, substantially reducing the number of buffers required for path balancing. Evaluated on multiple benchmark circuits, the approach achieves 100% timing convergence while reducing buffer insertion by 34% on average, at the cost of only a 4% reduction in operating frequency.

Technology Category

• Search and Optimization: Algorithm Configuration
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Machine Learning: Hardware-aware ML

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Agentic search

Abstract

Adiabatic Quantum-Flux-Parametron (AQFP) logic is an ultra-low-power superconducting logic family with energy consumption approaching the Shannon limit, making it attractive for quantum computing control and cryogenic computing systems. Traditional AQFP designs face significant physical design challenges due to strict gate-level clocking requirements and limited interconnect lengths, leading to substantial buffer overhead and difficult timing closure. Recently, delay-line clocking of AQFP has been proposed to improve timing margins and reduce latency by enabling more flexible clock scheduling. However, prior work has primarily focused on placement and latency minimization, while relying on fixed timing parameters that do not capture the frequency dependence of AQFP setup and hold constraints. To address this limitation, we propose a frequency-aware post-routing optimization framework that jointly optimizes clock period, latency, and timing slack under user-specified weighting. Experimental results across common benchmarks achieve 100% post-routing timing closure across a range of performance--latency--slack trade-offs. Our approach also automates phase-skipping, reducing path-balancing buffer insertion by 34% on average while only reducing operating frequency by 4%.

Problem

• AQFP
• delay line clocking
• timing closure
• frequency dependence
• setup and hold constraints

Innovation

• frequency-aware optimization
• delay-line clocking
• AQFP
• post-routing timing closure
• phase-skipping