High-Parallel FPGA-Based Discrete Simulated Bifurcation for Large-Scale Optimization

2025-10-14

AI Summary

Solving large-scale combinatorial optimization (CO) problems remains challenging due to exponential computational complexity. Method: This paper proposes an FPGA-based hardware acceleration framework for the quantum-inspired discrete Simulated Bifurcation (dSB) algorithm. Leveraging the Kerr-nonlinear parametric oscillator model, we design an open-source, configurable-parallelism fixed-point architecture, implemented on the AMD Kria KV260 SoM to solve Max-Cut and Knapsack problems with up to 256 variables. Contribution/Results: We present the first systematic evaluation of fixed-point arithmetic across dSB, binary SB (bSB), and hybrid SB (HbSB) algorithms, demonstrating its feasibility and significantly improving numerical efficiency and hardware compatibility. Experimental results show that our accelerator achieves low power consumption, high scalability, and real-time CO solving capability—establishing a novel paradigm for deploying CO solvers at the edge.

Technology Category

• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Search and Optimization: Mixed Discrete/Continuous Search
• Machine Learning: Hardware-aware ML

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

Combinatorial Optimization (CO) problems exhibit exponential complexity, making their resolution challenging. Simulated Adiabatic Bifurcation (aSB) is a quantum-inspired algorithm to obtain approximate solutions to largescale CO problems written in the Ising form. It explores the solution space by emulating the adiabatic evolution of a network of Kerr-nonlinear parametric oscillators (KPOs), where each oscillator represents a variable in the problem. The optimal solution corresponds to the ground state of this system. A key advantage of this approach is the possibility of updating multiple variables simultaneously, making it particularly suited for hardware implementation. To enhance solution quality and convergence speed, variations of the algorithm have been proposed in the literature, including ballistic (bSB), discrete (dSB), and thermal (HbSB) versions. In this work, we have comprehensively analyzed dSB, bSB, and HbSB using dedicated software models, evaluating the feasibility of using a fixed-point representation for hardware implementation. We then present an opensource hardware architecture implementing the dSB algorithm for Field-Programmable Gate Arrays (FPGAs). The design allows users to adjust the degree of algorithmic parallelization based on their specific requirements. A proof-of-concept implementation that solves 256-variable problems was achieved on an AMD Kria KV260 SoM, a low-tier FPGA, validated using well-known max-cut and knapsack problems.

Problem

• Developing FPGA-based discrete simulated bifurcation for large-scale combinatorial optimization
• Implementing quantum-inspired algorithms to solve exponential complexity Ising problems
• Creating configurable hardware architecture for parallel optimization on FPGAs

Innovation

• FPGA-based discrete simulated bifurcation hardware implementation
• Configurable parallelization for scalable combinatorial optimization
• Fixed-point representation enabling efficient FPGA resource usage