ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism

2025-10-11

AI Summary

CPU functional verification faces dual bottlenecks: inefficient stimulus generation and slow simulation. Front-end testing lacks microarchitectural awareness, leading to redundant test cases and poor coverage convergence; back-end FPGA-based simulation suffers from limited observability and high feedback latency. This paper proposes a full-stack co-verification framework comprising two key innovations: (1) a multi-agent stimulus engine that integrates microarchitectural knowledge and historical bug patterns to generate high-value, directed tests; and (2) a lightweight forward-snapshot mechanism coupled with an ISS-DUT decoupled co-simulation architecture, enabling a single-cycle-accurate instruction-set simulator to drive parallel FPGA-based verification. Experimental results demonstrate up to 17,536× speedup over RTL simulation and uncover multiple previously unknown bugs—including two publicly disclosed vulnerabilities—in a tape-out CPU. The framework significantly improves coverage closure efficiency and debugging agility.

Technology Category

• Cognitive Modeling & Cognitive Systems: Agent Architectures
• Machine Learning: Hardware-aware ML
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Web Mining and Content Analysis: Web data generation and simulation
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization

Abstract

Functional verification is a critical bottleneck in integrated circuit development, with CPU verification being especially time-intensive and labour-consuming. Industrial practice relies on differential testing for CPU verification, yet faces bottlenecks at nearly each stage of the framework pipeline: front-end stimulus generation lacks micro-architectural awareness, yielding low-quality and redundant tests that impede coverage closure and miss corner cases. Meanwhile, back-end simulation infrastructure, even with FPGA acceleration, often stalls on long-running tests and offers limited visibility, delaying feedback and prolonging the debugging cycle. Here, we present ISAAC, a full-stack, Large Language Model (LLM)-aided CPU verification framework with FPGA parallelism, from bug categorisation and stimulus generation to simulation infrastructure. To do so, we presented a multi-agent stimulus engine in ISAAC's front-end, infused with micro-architectural knowledge and historical bug patterns, generating highly targeted tests that rapidly achieve coverage goals and capture elusive corner cases. In ISAAC's back-end, we introduce a lightweight forward-snapshot mechanism and a decoupled co-simulation architecture between the Instruction Set Simulator (ISS) and the Design Under Test (DUT), enabling a single ISS to drive multiple DUTs in parallel. By eliminating long-tail test bottlenecks and exploiting FPGA parallelism, the simulation throughput is significantly improved. As a demonstration, we used ISAAC to verify a mature CPU that has undergone multiple successful tape-outs. Results show up to 17,536x speed-up over software RTL simulation, while detecting several previously unknown bugs, two of which are reported in this paper.

Problem

• Addresses CPU verification bottlenecks in stimulus generation and simulation
• Improves test quality via micro-architectural aware stimulus generation
• Accelerates verification through FPGA-parallel simulation architecture

Innovation

• LLM-aided multi-agent stimulus engine with micro-architectural knowledge
• Lightweight forward-snapshot mechanism for parallel simulation
• Decoupled co-simulation architecture driving multiple DUTs