PVU: Design and Implementation of a Posit Vector Arithmetic Unit (PVU) for Enhanced Floating-Point Computing in Edge and AI Applications

2025-03-03

AI Summary

IEEE 754 floating-point arithmetic suffers from low energy efficiency and limited precision in edge AI computing, while existing posit research focuses predominantly on scalar operations, lacking vector-level support. Method: This paper proposes PVU—the first posit-based vector unit—designed to accelerate vectorized AI workloads. We develop a parametric, modular hardware implementation in Chisel, featuring a posit vector arithmetic unit supporting addition, subtraction, multiplication, division, and dot product; we further introduce the first RISC-V instruction set extension for posit vector operations. Contribution/Results: Implemented on a Xilinx FPGA, PVU occupies only 65,407 LUTs and achieves 100% accuracy for all operations except division (95.84%). Convolution layer quantization experiments demonstrate substantial improvements in energy efficiency and practicality over both scalar posit and IEEE 754 baselines, effectively overcoming the performance bottleneck of existing formats under vectorized AI workloads.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Learning & Optimization for CV
• Humans and AI: Voting

Application Category

• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Responsible Web: Data and user privacy-enhancing technologies for the Web
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

With the rapid development of edge computing, artificial intelligence and other fields, the accuracy and efficiency of floating-point computing have become increasingly crucial. However, the traditional IEEE 754 floating-point system faces bottlenecks in energy consumption and computing accuracy, which have become major constraints. To address this issue, the Posit digital system characterized by adaptive accuracy, broader dynamic range and low hardware consumption has been put forward. Despite its widespread adoption, the existing research mainly concentrates on scalar computation, which is insufficient to meet the requirements of large-scale parallel data processing. This paper proposes, for the first time, a Posit Vector Arithmetic Unit (PVU) designed using the Chisel language. It supports vector operations such as addition, subtraction, multiplication, division, and dot product, thereby overcoming the limitations of traditional scalar designs and integrating the RISC-V instruction extension. The contributions of this paper include the efficient implementation of the vector arithmetic unit, the parametric and modular hardware design as well as the verification of the practical application of the positive digital system. This paper extracts the quantized data of the first convolutional layer for verification. Experiments indicate that the accuracy rate of the division operation is 95.84%, and the accuracy rate of the remaining operations is 100%. Moreover, the PVU is implemented with only 65,407 LUTs. Therefore, PVU has great potential as a new-generation floating-point computing platform in various fields.

Problem

• Addresses inefficiency in traditional floating-point computing for edge and AI applications.
• Proposes a Posit Vector Arithmetic Unit (PVU) for enhanced parallel data processing.
• Demonstrates PVU's high accuracy and low hardware consumption in practical applications.

Innovation

• Posit Vector Arithmetic Unit (PVU) design
• Chisel language for hardware implementation
• RISC-V instruction extension integration