CHRONOS: Compensating Hardware Related Overheads with Native Multi Timer Support for Real-Time Operating Systems

2025-03-03

AI Summary

To address the high overhead of global tick interrupts in real-time operating systems (RTOS), which degrades CPU utilization and real-time performance, this paper proposes a low-overhead tick management method leveraging coordinated multi-hardware timers. The core contribution is twofold: (1) the formulation of the first mixed-integer quadratically constrained programming (MIQCP) optimization model explicitly designed to maximize the greatest common divisor (GCD) of task periods, enabling intelligent mapping of tasks onto multiple hardware timers; and (2) a GCD-driven asynchronous interrupt scheduling mechanism that minimizes the frequency of global tick interrupts. A customized kernel implementation on FreeRTOS demonstrates that the approach reduces peak tick interrupt overhead by approximately 10× and average overhead by ~6×, significantly improving both system CPU utilization and the timing precision of real-time task releases.

Technology Category

• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Constraint Satisfaction and Optimization: Mixed Discrete/Continuous Optimization
• Search and Optimization: Mixed Discrete/Continuous Search

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Security and Privacy: Large-scale security measurements

Abstract

The management of timing constraints in a real-time operating system (RTOS) is usually realized through a global tick counter. This counter acts as the foundational time unit for all tasks in the systems. In order to establish a connection between a tick and an amount of elapsed time in the real world, often this tick counter is periodically incremented by a hardware timer. At a fixed interval, this timer generates an interrupt that increments the counter. In an RTOS, jobs can only become ready upon a timer tick. That means, during a tick interrupt, the tick counter will be incremented, jobs will be released, and potentially, a scheduling decision will be conducted to select a new job to be run. As this process naturally uses some processing time, it is beneficial regarding the system utilization to minimize the time spent in tick interrupts. In modern microcontrollers, multiple hardware timers are often available. To utilize multiple timers to reduce the overhead caused by tick interrupts, multiple methods are introduced in this paper. The number of interrupts that are triggered by these timers can then be reduced by mapping tasks to timers in such a manner that the greatest common divisor (GCD) of all task periods in a subset is maximized, and the GCD is adopted as the interrupt interval of the timer. To find an optimal mapping of tasks to timers, an MIQCP-model is presented that minimizes the overall number of tick interrupts that occur in a system, while ensuring a correct task release behavior. The presented methods are implemented in FreeRTOS and evaluated on an embedded system. The evaluation of the methods show, that compared to the baseline implementation in FreeRTOS that uses a single timer with a fixed period, the presented methods can provide a significant reduction in overhead of up to $approx10 imes$ in peak and up to $approx 6 imes$ in average.

Problem

• Reducing tick interrupt overhead in RTOS using multiple hardware timers.
• Optimizing task-to-timer mapping to minimize system tick interrupts.
• Implementing and evaluating multi-timer support in FreeRTOS for efficiency.

Innovation

• Utilizes multiple hardware timers for RTOS
• Maximizes GCD of task periods for efficiency
• Implements MIQCP-model to minimize tick interrupts