A Faster and More Reliable Middleware for Autonomous Driving Systems

2025-10-13

AI Summary

To address high control-loop latency and insufficient real-time performance in high-speed autonomous driving—caused by serialization, memory copying, and discovery overhead in ROS 2’s multi-node deployment on a single compute unit—this paper proposes a kernel-space shared-memory middleware tailored for in-vehicle data pipelines. Our approach innovatively integrates native memory layout preservation, lock-free double buffering, and freshness-prioritized scheduling, augmented with writer-side heartbeat signaling, sequence-number–based ordering, and optional checksum validation. Fully compatible with the ROS 2 ecosystem, integration requires only four lines of code. Evaluation on Jetson Orin Nano demonstrates a 95% reduction in average latency and a 96% reduction in tail latency. In vehicle tests, localization frequency increases from 7.5 Hz to 9.5 Hz, and emergency braking distance shortens by 4.14 m—significantly enhancing both system real-time performance and operational safety.

Technology Category

• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Intelligent Robots: Localization, Mapping, and Navigation
• Computer Vision: Vision for Robotics & Autonomous Driving

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications
• Security and Privacy: Data transparency and provenance
• Responsible Web: Machine-in-the-loop, human agency and autonomy

Abstract

Ensuring safety in high-speed autonomous vehicles requires rapid control loops and tightly bounded delays from perception to actuation. Many open-source autonomy systems rely on ROS 2 middleware; when multiple sensor and control nodes share one compute unit, ROS 2 and its DDS transports add significant (de)serialization, copying, and discovery overheads, shrinking the available time budget. We present Sensor-in-Memory (SIM), a shared-memory transport designed for intra-host pipelines in autonomous vehicles. SIM keeps sensor data in native memory layouts (e.g., cv::Mat, PCL), uses lock-free bounded double buffers that overwrite old data to prioritize freshness, and integrates into ROS 2 nodes with four lines of code. Unlike traditional middleware, SIM operates beside ROS 2 and is optimized for applications where data freshness and minimal latency outweigh guaranteed completeness. SIM provides sequence numbers, a writer heartbeat, and optional checksums to ensure ordering, liveness, and basic integrity. On an NVIDIA Jetson Orin Nano, SIM reduces data-transport latency by up to 98% compared to ROS 2 zero-copy transports such as FastRTPS and Zenoh, lowers mean latency by about 95%, and narrows 95th/99th-percentile tail latencies by around 96%. In tests on a production-ready Level 4 vehicle running Autoware.Universe, SIM increased localization frequency from 7.5 Hz to 9.5 Hz. Applied across all latency-critical modules, SIM cut average perception-to-decision latency from 521.91 ms to 290.26 ms, reducing emergency braking distance at 40 mph (64 km/h) on dry concrete by 13.6 ft (4.14 m).

Problem

• ROS 2 middleware introduces high latency in autonomous driving systems
• Shared memory transport reduces data copying and serialization overhead
• Optimizing for data freshness and minimal latency over guaranteed completeness

Innovation

• Shared-memory transport for intra-host autonomous vehicle pipelines
• Lock-free double buffers prioritizing data freshness over completeness
• Reduces latency up to 98% compared to ROS 2 transports