RePart: Efficient Hypergraph Partitioning with Logic Replication Optimization for Multi-FPGA System

2026-04-01

AI Summary

Existing multi-FPGA hypergraph partitioning approaches focus solely on minimizing cut size while ignoring network topology and suffer from low resource utilization due to overly conservative resource balancing strategies. To address these limitations, this work proposes RePart, a multilevel hypergraph partitioning framework tailored for multi-FPGA systems, which enhances partition quality through three synergistic innovations: FPGA-aware dynamic coarsening, heat-value-guided node assignment, and a refinement mechanism supporting logic replication and deletion. Experimental results demonstrate that RePart achieves a 52.3% average reduction in total wirelength and an 11.1× speedup over state-of-the-art partitioners and competition-winning solutions on the Titan23 and EDA Elite Challenge benchmarks.

Abstract

Multi-FPGA systems (MFS) are widely adopted for VLSI emulation and rapid prototyping. In an MFS, FPGAs connect only to a limited number of neighbors through bandwidth-constrained links, so inter-FPGA communication cost depends on network topology. This setting exposes two fundamental limitations of existing MFS-aware partitioning methods: conventional hypergraph partitioners focus solely on cut size and ignore topological structure, and they leave substantial FPGA resources unused due to conservative balance margins. We present RePart, a fully customized multilevel hypergraph partitioning framework for MFS that integrates logic replication with topology-aware optimization. RePart introduces three coordinated innovations across the multilevel pipeline: FPGA-aware dynamic coarsening, heat-value guided assignment, and replication-deletion supported refinement. Extensive experiments on the Titan23 and EDA Elite Challenge Contest benchmarks show that RePart reduces total hop distance by 52.3% on average over state-of-the-art hypergraph partitioners with an 11.1x speedup, and outperforms the EDA Elite Challenge winners. Code is available at: https://github.com/Welement-zyf/RePart.

Problem

• hypergraph partitioning
• multi-FPGA system
• logic replication
• topology-aware optimization
• resource utilization

Innovation

• hypergraph partitioning
• logic replication
• topology-aware optimization
• multi-FPGA system
• multilevel framework