HiVeGen - Hierarchical LLM-based Verilog Generation for Scalable Chip Design

2024-12-06

arXiv.org

AI Summary

Large language models (LLMs) often generate Verilog code lacking hierarchical structure, leading to frequent hallucinations and poor maintainability in complex hardware designs—especially domain-specific accelerators (DSAs). To address this, we propose the first hierarchical LLM-driven framework for HDL generation, integrating hierarchy-aware prompting, weight-guided code reuse, and real-time human-in-the-loop error correction. Our approach embeds design space exploration (DSE) directly into the LLM-based Verilog synthesis pipeline—enabling systematic trade-off analysis during code generation. Technically, it combines task decomposition, DSE-guided prompt engineering, vector-retrieval-enhanced code reuse, and interactive feedback-based fine-tuning, all implemented end-to-end on mainstream open-source LLMs. Experiments demonstrate a substantial reduction in hallucination rate, a 3.2× increase in module reuse, a 67% decrease in manual correction effort, and an overall functional correctness rate of 91.4%.

Technology Category

• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Machine Learning: Large Multimodal Models (LMMs)
• Humans and AI: Human-in-the-loop Machine Learning

Application Category

• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Search and Retrieval-Augmented AI: Search Tool Learning with LLM: Teaching LLMs to invoke search and make use of retrieved information
• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions

Abstract

With Large Language Models (LLMs) recently demonstrating impressive proficiency in code generation, it is promising to extend their abilities to Hardware Description Language (HDL). However, LLMs tend to generate single HDL code blocks rather than hierarchical structures for hardware designs, leading to hallucinations, particularly in complex designs like Domain-Specific Accelerators (DSAs). To address this, we propose HiVeGen, a hierarchical LLM-based Verilog generation framework that decomposes generation tasks into LLM-manageable hierarchical submodules. HiVeGen further harnesses the advantages of such hierarchical structures by integrating automatic Design Space Exploration (DSE) into hierarchy-aware prompt generation, introducing weight-based retrieval to enhance code reuse, and enabling real-time human-computer interaction to lower error-correction cost, significantly improving the quality of generated designs.

Problem

• Generates hierarchical Verilog code for scalable chip design
• Reduces hallucinations in complex hardware design generation
• Enables modular code reuse and human-computer interaction

Innovation

• Hierarchical decomposition of Verilog generation tasks
• Automatic design space exploration in prompts
• Weight-based retrieval for enhanced code reuse