Recurrent CircuitSAT Sampling for Sequential Circuits

2025-02-28

AI Summary

In constraint-random verification (CRV), jointly generating input stimuli and the minimal valid clock period for sequential circuits faces challenges including uncontrollable SAT solving behavior and unsatisfiability arising from fixed-period unrolling. This paper proposes the first differentiable CircuitSAT framework: it models sequential circuits as recurrent differentiable logic and reformulates joint stimulus-and-period generation as a supervised multi-output regression task. Gradient-based optimization enables adaptive clock period determination, while GPU-accelerated tensor computation and recurrent logic unrolling are integrated for efficiency. Evaluated on ISCAS-89 and ITC’99 benchmarks, our approach achieves up to 105.1× speedup over conventional SAT-based samplers, significantly improving solution diversity and functional coverage.

Technology Category

• Constraint Satisfaction and Optimization: Satisfiability
• Search and Optimization: Sampling/Simulation-based Search
• Reasoning under Uncertainty: Stochastic Optimization

Application Category

• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Security and Privacy: Large-scale security measurements
• Graph Algorithms and Modeling for the Web: Representation, reconstruction, and subgraph or motif discovery in Web-related graphs

Abstract

In this work, we introduce a novel GPU-accelerated circuit satisfiability (CircuitSAT) sampling technique for sequential circuits. This work is motivated by the requirement in constrained random verification (CRV) to generate input stimuli to validate the functionality of digital hardware circuits. A major challenge in CRV is generating inputs for sequential circuits, along with the appropriate number of clock cycles required to meet design constraints. Traditional approaches often use Boolean satisfiability (SAT) samplers to generate inputs by unrolling state transitions over a fixed number of clock cycles. However, these methods do not guarantee that a solution exists for the given number of cycles. Consequently, producing input stimuli together with the required clock cycles is essential for thorough testing and verification. Our approach converts the logical constraints and temporal behavior of sequential circuits into a recurrent CircuitSAT problem, optimized via gradient descent to efficiently explore a diverse set of valid solutions, including their associated number of clock cycles. By operating directly on the circuit structure, our method reinterprets the sampling process as a supervised multi-output regression task. This differentiable framework enables independent element-wise operations on each tensor element, facilitating parallel execution during learning. As a result, we achieve GPU-accelerated sampling with substantial runtime improvements (up to 105.1x) over state-of-the-art heuristic samplers. We demonstrate the effectiveness of our method through extensive evaluations on circuit problems from the ISCAS-89 and ITC'99 benchmark suites.

Problem

• Generates input stimuli for sequential circuit verification.
• Determines required clock cycles for design constraints.
• Improves runtime with GPU-accelerated CircuitSAT sampling.

Innovation

• GPU-accelerated CircuitSAT sampling technique
• Recurrent CircuitSAT problem via gradient descent
• Supervised multi-output regression for parallel execution