π€ AI Summary
This work addresses the tight coupling between circuit cutting logic and execution scheduling in existing quantum circuit partitioning frameworks, which hinders high-performance computing (HPC) systems from applying mature resource management strategies to NISQ workloads. To overcome this limitation, the authors propose DQR, a runtime framework that, for the first time, abstracts quantum circuit fragments as first-class schedulable units. By introducing backend-agnostic structured descriptors, a wave-based coordinator, and a non-blocking polling mechanism, DQR decouples cutting from scheduling. The framework enables transparent fault tolerance, heterogeneous backend integration, and hybrid local-cloud scheduling. Experimental results demonstrate significant reductions in job completion time on 32-qubit hardware-efficient ansatz circuits, with coordination overhead accounting for only 5% in deep circuits, and automatic migration of failed fragments to classical simulators, confirming its high scalability and flexibility.
π Abstract
Hybrid High-performance Computing (HPC)-quantum workloads based on circuit cutting decompose large quantum circuits into independent fragments, but existing frameworks tightly couple cutting logic to execution orchestration, preventing HPC centers from applying mature resource management policies to Noisy Intermediate-Scale Quantum (NISQ) workloads. We present DQR (Dynamic Queue Router), a runtime framework that bridges this gap by treating circuit fragments as first-class schedulable units. The framework introduces a backend-agnostic fragment descriptor to expose structural properties without requiring execution layers to parse quantum code, a wave-based coordinator that achieves pipeline concurrency via non-blocking polling, and a production-ready implementation on the CESGA Qmio supercomputer integrating both QPUs local on-premises (Qmio) and remote cloud (IBM Torino) backends. Experiments on a 32-qubit Hardware-Efficient Ansatz (HEA) circuit demonstrate not only makespan improvements over a monolithic CPU baseline but also transparent per-fragment failover recovery-specifically rerouting tasks from the local QPU to classical simulators upon encountering hardware-level incompatibilities-without pipeline restart. For deeper circuits, the coordination residual accounts for only 5% of the total execution time, highlighting the framework's scalability. These results show that DQR enables HPC centers to integrate NISQ workloads into existing production infrastructure while preserving the flexibility to adopt improved cutting algorithms or heterogeneous backend technologies.