FPGA-Accelerated SpeckleNN with SNL for Real-time X-ray Single-Particle Imaging

📅 2025-02-27
📈 Citations: 0
Influential: 0
📄 PDF

career value

222K/year
🤖 AI Summary
To address the challenges of real-time speckle pattern classification—namely, high latency and poor adaptability—in X-ray free-electron laser (XFEL) single-particle imaging (SPI), this work proposes a field-programmable gate array (FPGA)-oriented dynamically reconfigurable inference architecture. Our approach introduces model-specific hardware design coupled with a Synapse-Neuron-Layer (SNL) dynamic weight reloading mechanism, eliminating redundant synthesis and enabling millisecond-scale post-training model deployment. Combined with parameter pruning and latent-space compression, it achieves a 98.8% reduction in model parameters. Implemented on a KCU1500 FPGA operating at 200 MHz, the architecture delivers an inference latency of 45.015 μs—8.9× faster than GPU-based inference—and consumes only 9.4 W, yielding a 7.8× improvement in energy efficiency, while maintaining bounded resource utilization. To our knowledge, this is the first work to realize low-latency, high-energy-efficiency, and adaptive real-time speckle classification in XFEL-SPI, significantly enhancing experimental throughput and robustness.

Technology Category

Application Category

📝 Abstract
We implement a specialized version of our SpeckleNN model for real-time speckle pattern classification in X-ray Single-Particle Imaging (SPI) using the SLAC Neural Network Library (SNL) on an FPGA. This hardware is optimized for inference near detectors in high-throughput X-ray free-electron laser (XFEL) facilities like the Linac Coherent Light Source (LCLS). To fit FPGA constraints, we optimized SpeckleNN, reducing parameters from 5.6M to 64.6K (98.8% reduction) with 90% accuracy. We also compressed the latent space from 128 to 50 dimensions. Deployed on a KCU1500 FPGA, the model used 71% of DSPs, 75% of LUTs, and 48% of FFs, with an average power consumption of 9.4W. The FPGA achieved 45.015us inference latency at 200 MHz. On an NVIDIA A100 GPU, the same inference consumed ~73W and had a 400us latency. Our FPGA version achieved an 8.9x speedup and 7.8x power reduction over the GPU. Key advancements include model specialization and dynamic weight loading through SNL, eliminating time-consuming FPGA re-synthesis for fast, continuous deployment of (re)trained models. These innovations enable real-time adaptive classification and efficient speckle pattern vetoing, making SpeckleNN ideal for XFEL facilities. This implementation accelerates SPI experiments and enhances adaptability to evolving conditions.
Problem

Research questions and friction points this paper is trying to address.

Real-time speckle pattern classification in X-ray SPI
Optimized FPGA inference for high-throughput XFEL facilities
Achieved significant speedup and power reduction over GPU
Innovation

Methods, ideas, or system contributions that make the work stand out.

FPGA-accelerated SpeckleNN for real-time imaging
Model optimization reduces parameters significantly
Dynamic weight loading enables fast deployment
🔎 Similar Papers
No similar papers found.
Abhilasha Dave
Abhilasha Dave
Stanford
Machine Learning Hardware AcceleratorsMachine LearningHigh Performance Computer Architecture
C
Cong Wang
SLAC National Accelerator Laboratory, Menlo Park, CA, USA
J
James Russell
SLAC National Accelerator Laboratory, Menlo Park, CA, USA
R
Ryan Herbst
SLAC National Accelerator Laboratory, Menlo Park, CA, USA
J
Jana Thayer
SLAC National Accelerator Laboratory, Menlo Park, CA, USA