Late Breaking Results: The Art of Beating the Odds with Predictor-Guided Random Design Space Exploration

2025-02-25

AI Summary

To address the challenge of jointly optimizing performance, power, and area in Majority-Inverter Graph (MIG) circuit synthesis, this paper proposes a predictor-guided stochastic exploration method that integrates next-state prediction models with controlled random sampling within an iterative selection framework for efficient design-space exploration. We first reveal a non-monotonic relationship between prediction accuracy and synthesis quality, establishing the novel paradigm of “beneficial randomness”—moderate stochasticity enables escape from local optima. Evaluated on the EPFL benchmark suite, our approach achieves up to 14× speedup and reduces average MIG area by 20.94%, significantly outperforming state-of-the-art synthesis tools. The core innovation lies in the synergistic integration of predictive modeling and controllable stochasticity, opening a new data-driven and stochastic-optimization pathway for logic synthesis.

Technology Category

• Reasoning under Uncertainty: Stochastic Optimization
• Machine Learning: Probabilistic Circuits and Graphical Models
• Search and Optimization: Mixed Discrete/Continuous Search

Application Category

• Graph Algorithms and Modeling for the Web: Algorithms and analysis for incomplete, noisy, or partially observed Web-related graphs
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

This work introduces an innovative method for improving combinational digital circuits through random exploration in MIG-based synthesis. High-quality circuits are crucial for performance, power, and cost, making this a critical area of active research. Our approach incorporates next-state prediction and iterative selection, significantly accelerating the synthesis process. This novel method achieves up to 14x synthesis speedup and up to 20.94% better MIG minimization on the EPFL Combinational Benchmark Suite compared to state-of-the-art techniques. We further explore various predictor models and show that increased prediction accuracy does not guarantee an equivalent increase in synthesis quality of results or speedup, observing that randomness remains a desirable factor.

Problem

• Improving combinational digital circuits
• Accelerating MIG-based synthesis process
• Exploring predictor models in synthesis

Innovation

• Predictor-guided random exploration
• Next-state prediction and iterative selection
• MIG minimization optimization