Physically-Aware Preemptive Virtual Channels for Deadlock-Free AXI Networks-on-Chip

2026-07-01

AI Summary

This work addresses the risk of deadlock induced by read-write traffic dependencies in the AXI4 protocol at network endpoints, even when the underlying routing algorithm is inherently deadlock-free. To overcome the trade-off between resource overhead and design complexity in conventional multi-plane or virtual channel approaches, the paper proposes a physically aware preemptive virtual channel architecture. By leveraging AXI4 traffic classification and integrating lightweight virtual channels with physical link characteristics, the proposed method ensures deadlock freedom while substantially improving resource efficiency. Experimental results demonstrate that, compared to multi-plane designs, the approach reduces link resource usage by 76%, increases router area by only 3%, and maintains the original operating frequency.

Abstract

As many-core Systems-on-Chip (SoCs) continue to scale, Networks-on-Chip (NoCs) must sustain increasingly high memory bandwidth while preserving deadlock freedom. In AXI4 systems, protocol-level dependencies between read and write traffic can create circular waits at the network endpoints, even when the routing algorithm itself is deadlock-free. Decoupling these traffic classes avoids such dependencies, but exposes a key implementation trade-off: multiplane NoCs duplicate wide physical links and increase routing pressure, whereas conventional Virtual Channel (VC) routers add substantial control complexity, area, and timing overhead. This work revisits this trade-off for modern wide-link NoCs. We evaluate four deadlock-free AXI4 traffic-class separation schemes: a multiplane baseline and three lightweight VC-based designs. Among these designs, we propose Preemptive VCs, a physically-aware architecture that can save up to 76% of link resources with comparable frequency and only 3% router area overhead relative to the multiplane design.

Problem

• Deadlock-Free
• AXI Networks-on-Chip
• Virtual Channels
• Traffic-Class Separation
• Many-core SoCs

Innovation

• Preemptive Virtual Channels
• Deadlock-Free NoC
• AXI4
• Physically-Aware Design
• Traffic-Class Separation