🤖 AI Summary
Current quantum hardware exhibits highly spatially non-uniform noise, yet existing circuit cutting methods do not systematically account for such heterogeneous noise profiles, leading to exponentially growing sampling overhead. This work proposes a hardware noise-aware circuit cutting framework that explicitly incorporates spatial noise non-uniformity into the cutting strategy for the first time. By unifying gate and wire cutting within a single modeling framework and leveraging real-device noise maps to optimize subcircuit allocation and execution constraints, the method achieves exponential overhead reduction while maintaining low-noise alignment. Notably, it requires only minor relaxation of device constraints to avoid high-noise regions. Experiments demonstrate an average 5–54× reduction in required circuit executions on 20-qubit circuits and, for the first time, enable feasible cutting of 50-qubit circuits and application-level benchmarks, substantially outperforming conventional strategies.
📝 Abstract
Noise in contemporary quantum hardware is highly non-uniform across qubits and couplers, giving rise to localized low-noise "islands" within otherwise noisy device topologies. As quantum workloads scale, executions are increasingly forced to traverse high-noise regions, degrading algorithmic fidelity. Circuit cutting provides a route to circumvent such regions by decomposing large circuits into smaller subcircuits, but its practicality is limited by exponential sampling overhead and the lack of systematic guidance on how cut strategies should align with heterogeneous hardware noise. In this work, we present a hardware-noise-aware circuit cutting framework that explicitly exploits the spatial non-uniformity of noise in quantum devices. Rather than proposing a new cut-finding algorithm, we formalize the problem of device-constraint selection under realistic hardware noise and show that this choice critically determines both execution overhead and effective noise. Using a unified gate- and wire-cutting formulation, we demonstrate that small, hardware-informed relaxations in the device constraint yield exponential reductions in execution overhead while preserving alignment with low-noise hardware regions. Across representative workloads, our method achieves an average reduction in the number of circuit executions ranging from 5-54x for 20-qubit circuits, and enables tractable circuit cutting for 50-qubit circuits and application-level benchmarks where conventional strategies incur prohibitive overhead. These results establish noise-aware device-constraint selection as a necessary ingredient for making circuit cutting resource-efficient and practically deployable on contemporary quantum hardware.