TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog

2026-04-26

AI Summary

This work addresses the challenge of rapidly predicting post-synthesis timing metrics—specifically worst negative slack (WNS) and total negative slack (TNS)—directly from RTL without EDA tool intervention. The authors propose the first retrieval-augmented, two-stage large language model (LLM) framework: in the first stage, a fine-tuned LLM generates path-level timing hints and extracts structured key features; in the second stage, k-nearest neighbor retrieval identifies similar modules, and a lightweight regression head, guided by diagonal anchor vectors, predicts the final timing metrics. This approach requires fine-tuning only a small regression head to adapt to new technology libraries and PVT corners, significantly enhancing generalization and deployment efficiency. Evaluated on VerilogEval, the method achieves Pearson correlation coefficients of 0.91 for WNS and 0.97 for TNS (with MAPEs of 12% and 16%, respectively) and offers 1.3–1.6× faster inference than existing methods. A new dataset comprising 60,000 modules is also publicly released.

Technology Category

• Planning, Routing, and Scheduling: Planning with Language Models
• Machine Learning: Large Multimodal Models (LMMs)
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language

Application Category

• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Web Mining and Content Analysis: Large pretrained models with web data

Abstract

Early, tool-free prediction of post-synthesis timing remains a key obstacle to rapid RTL iteration. We introduce TimingLLM, a two-stage retrieval-augmented LLM pipeline that estimates worst negative slack (WNS) and total negative slack (TNS) directly from Verilog. Stage 1 is a fine-tuned LLM that acts as a compact post-synthesis timing oracle, producing path-level arrivals/required times that are summarized into lightweight structural-timing cues (e.g., bag-of-gates counts, critical-path depth, gate-type patterns). Stage 2 is an LLM-based regressor that predicts WNS/TNS and applies a learned diagonal steering vector at the last transformer block, computed from the k nearest timing-labeled modules in a disjoint retrieval bank. On VerilogEval, TimingLLM attains R_WNS = 0.91 (MAPE 12%) and R_TNS=0.97 (MAPE 16%) while running 1.3-1.6 times faster than prior methods. Training uses a new 60k-module Verilog corpus with synthesis reports, which we will release. After training once, TimingLLM can be adapted to new technology libraries and PVT corners by refitting only a small regression head on 1000 labeled modules per setting, consistently outperforming state-of-the-art baselines.

Problem

• timing prediction
• pre-synthesis
• Verilog
• WNS
• TNS

Innovation

• Retrieval-Augmented LLM
• Pre-synthesis Timing Prediction
• Worst Negative Slack (WNS)
• Technology Library Adaptation
• Structural-Timing Cues