A Multiplication-Free Spike-Time Learning Algorithm and its Efficient FPGA Implementation for On-Chip SNN Training

2026-04-25

AI Summary

This work addresses the challenge of efficiently implementing on-chip supervised training for spiking neural networks (SNNs) on resource-constrained edge devices by proposing a multiplication-free, fully event-driven digital training architecture. Leveraging spike-timing-based encoding and fixed-point integer arithmetic, the approach eliminates floating-point operations and explicit gradient storage, enabling an efficient pipelined implementation on a Xilinx Artix-7 FPGA. As the first fully multiplication-free on-chip SNN training framework, it achieves 96.5% accuracy on MNIST and 84.8% on Fashion-MNIST, significantly reducing computational and memory overhead while maintaining high speed, low hardware resource utilization, and superior energy efficiency.

Technology Category

• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Machine Learning: Learning on the Edge & Model Compression
• Computer Vision: Learning & Optimization for CV

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments

Abstract

Spiking Neural Networks (SNNs) offer a biologically inspired foundation for low-power, event-driven intelligence, yet their direct on-chip supervised training remains a key hardware challenge. This paper presents a multiplication-free, spike-time-based learning algorithm specifically designed for efficient FPGA realization. The proposed approach eliminates floating-point arithmetic and explicit gradient storage, enabling a fully event-driven, digital training pipeline. Implemented on a Xilinx Artix-7 FPGA, the architecture achieves high operating speed and minimal resource usage while maintaining competitive accuracy. These results demonstrate that the learning algorithm effectively maps onto reconfigurable hardware, achieving both computational and energy efficiency. Software simulations further validate scalability, with 96.5\% and 84.8\% accuracy on MNIST and Fashion-MNIST. With its spike-driven and multiplier-free operation, the proposed framework delivers a practical and scalable hardware solution for real-time, on-chip SNN learning in edge environments.

Problem

• Spiking Neural Networks
• on-chip training
• hardware efficiency
• edge computing
• supervised learning

Innovation

• multiplication-free
• spike-time learning
• on-chip training
• FPGA implementation
• event-driven