From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation

2026-04-24

AI Summary

This work addresses the limitations of existing approaches to automatic SystemVerilog Assertion (SVA) generation—namely, erroneous signal references, missing temporal constraints, and the absence of formal correctness guarantees—by introducing ProofLoop, a tool-augmented ReAct agent that integrates a formal verification solver into the large language model reasoning loop. ProofLoop employs a two-stage pipeline: it first retrieves design context using EDA tools and an AST-based vector database, then iteratively refines assertions through structural queries in JasperGold and multi-round feedback from formal verification. Evaluated on the FVEval Design2SVA benchmark, ProofLoop achieves 93.7% syntactic correctness and 82.0% functional correctness. Ablation studies confirm that each component contributes significantly and orthogonally to overall performance.

Technology Category

• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Multiagent Systems: Adversarial Agents

Application Category

• Search and Retrieval-Augmented AI: Agentic search
• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems

Abstract

SystemVerilog Assertions (SVA) are essential for formal verification of digital hardware, yet their manual creation demands significant expertise in both the design under verification and temporal logic. Recent studies have explored using large language models (LLMs) to automate SVA generation, but existing approaches suffer from incorrect signal references, missing timing constraints, and lack of formal correctness guarantees. This paper presents ProofLoop, a tool-augmented ReAct agent that generates SVA from natural-language specifications using a solver-in-the-loop approach. The agent operates in two phases: Phase A autonomously gathers design context by invoking EDA and formal tools, including semantic search over an AST-indexed vector database and JasperGold structural queries, while Phase B generates SVA and iteratively refines it using JasperGold formal proof feedback over up to fixed (here 3) verification rounds. We evaluate ProofLoop on FVEval Design2SVA design benchmarks and demonstrate that this framework can achieve 93.7% syntax correctness and 82.0% functional correctness. An ablation study confirms that each component, i.e., retrieval-augmented generation (RAG), JasperGold tools, and the verification loop contributes significantly (and orthogonally).

Problem

• SystemVerilog Assertions
• formal verification
• large language models
• temporal logic
• RTL assertion generation

Innovation

• tool-augmented ReAct agent
• solver-in-the-loop
• retrieval-augmented generation
• formal verification
• SystemVerilog Assertions