Secure eFPGA-Enabled Edge LLM Inference: Architectural and Hardware Countermeasures

2026-04-24

AI Summary

Transformer models deployed at the edge often rely on ASIC accelerators, rendering them vulnerable to side-channel attacks, fault injection, and hardware supply chain threats that can lead to model leakage or distorted inference. This work proposes a heterogeneous architecture that integrates ASICs with embedded FPGA (eFPGA) fabric, uniquely leveraging eFPGA for security enhancement of edge-based large language models while preserving ASIC-level energy efficiency and performance. By exploiting the reconfigurable logic of eFPGA, the architecture enables runtime security monitoring, side-channel mitigation, and hardware-level dynamic patching. This approach effectively counters both runtime and supply chain threats, substantially improving the overall system security without compromising computational efficiency.

Technology Category

• Machine Learning: Learning on the Edge & Model Compression
• Natural Language Processing: Safety and Robustness
• Computer Vision: Large Vision Models

Application Category

• Security and Privacy: Security and privacy of machine learning and AI applications
• Search and Retrieval-Augmented AI: Large language models for search
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

Edge deployment of transformer-based models increasingly relies on ASIC accelerators due to their high performance and energy efficiency, achieved through optimized dataflows, specialized architectures, low-bitwidth computation, and efficient memory hierarchies. However, these advantages come with significant security vulnerabilities. ASIC-based DNN accelerators are susceptible to side-channel attacks (e.g., power, electromagnetic, and timing analysis) and fault injection attacks (e.g., voltage manipulation, clock glitches, and memory perturbations), which can lead to model extraction or compromised inference integrity. Furthermore, threats introduced during design and fabrication, such as hardware Trojans or untrusted third-party IPs, further expand the attack surface. To address these challenges, we explore a hybrid ASIC+eFPGA architecture that combines the efficiency of ASICs with the flexibility of reconfigurable logic. The integrated eFPGA enables security-oriented mechanisms such as adaptive runtime monitoring, side-channel mitigation and post-deployment patching. By leveraging these capabilities, the proposed approach enhances system resilience against both runtime and supply-chain attacks, while preserving the performance benefits of ASIC-based transformer inference.

Problem

• side-channel attacks
• fault injection attacks
• hardware Trojans
• ASIC security
• edge LLM inference

Innovation

• eFPGA
• ASIC
• side-channel mitigation
• runtime monitoring
• hardware security