🤖 AI Summary
Current EDA tools for quantum chips suffer from incomplete coverage, low automation, poor process integration, and limited scalability. To address these challenges, this project proposes a full-stack EDA framework tailored for superconducting quantum chips. It introduces a novel, extensible architecture supporting bidirectional device–process mapping—unprecedented in prior work—and integrates parametric modeling, automated placement and routing, process-design-rule-driven mapping, and an interactive scripting engine. The framework accommodates diverse quantum devices and provides dual interfaces—command-line and script-based—to significantly lower the usability barrier. Experimental evaluation demonstrates over 40% reduction in design cycle time, automation exceeding 90%, and 100% functional correctness in tape-out validation. The framework has already enabled the development of multiple superconducting quantum processor prototypes.
📝 Abstract
Electronic Design Automation (EDA) plays a crucial role in classical chip design and significantly influences the development of quantum chip design. However, traditional EDA tools cannot be directly applied to quantum chip design due to vast differences compared to the classical realm. Several EDA products tailored for quantum chip design currently exist, yet they only cover partial stages of the quantum chip design process instead of offering a fully comprehensive solution. Additionally, they often encounter issues such as limited automation, steep learning curves, challenges in integrating with actual fabrication processes, and difficulties in expanding functionality. To address these issues, we developed a full-stack EDA tool specifically for quantum chip design, called EDA-Q. The design workflow incorporates functionalities present in existing quantum EDA tools while supplementing critical design stages such as device mapping and fabrication process mapping, which users expect. EDA-Q utilizes a unique architecture to achieve exceptional scalability and flexibility. The integrated design mode guarantees algorithm compatibility with different chip components, while employing a specialized interactive processing mode to offer users a straightforward and adaptable command interface. Application examples demonstrate that EDA-Q significantly reduces chip design cycles, enhances automation levels, and decreases the time required for manual intervention. Multiple rounds of testing on the designed chip have validated the effectiveness of EDA-Q in practical applications.