An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks

2026-03-17

AI Summary

This work addresses the challenges of deploying spiking neural networks (SNNs) on FPGAs—namely high computational overhead, substantial memory consumption, and limited architectural flexibility—by proposing a compact system-on-chip (SoC) architecture that integrates a RISC-V controller with an event-driven SNN core. For the first time, a self-contained temporally coded SNN system is implemented on a Xilinx Artix-7 FPGA. The design achieves significant reductions in computation and memory usage through binary-weight encoding that replaces multiplications with bitwise operations, a spike-timing scheduler, and the omission of non-informative events. Experimental results demonstrate classification accuracies of 97.0% on MNIST and 88.3% on Fashion-MNIST, along with a 16× reduction in weight storage, while maintaining real-time performance and energy efficiency.

Technology Category

• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Machine Learning: Learning on the Edge & Model Compression
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web

Abstract

Spiking Neural Networks (SNNs) offer high energy efficiency and event-driven computation, ideal for low-power edge AI. Their hardware implementation on FPGAs, however, faces challenges due to heavy computation, large memory use, and limited flexibility. This paper proposes a compact System-on-Chip (SoC) architecture for temporal-coding SNNs, integrating a RISC-V controller with an event-driven SNN core. It replaces multipliers with bitwise operations using binarized weights, includes a spike-time sorter for active spikes, and skips noninformative events to reduce computation. The architecture runs fully on a Xilinx Artix-7 FPGA, achieving up to 16x memory reduction for weights and lowering computational overhead and latency, with 97.0% accuracy on MNIST and 88.3% on FashionMNIST. This self-contained design provides an efficient, scalable platform for real-time neuromorphic inference at the edge.

Problem

• Spiking Neural Networks
• FPGA implementation
• energy efficiency
• temporal coding
• edge AI

Innovation

• Temporal-coding SNN
• RISC-V SoC
• Binarized weights
• Event-driven architecture
• FPGA neuromorphic computing