🤖 AI Summary
This work investigates a fundamental trade-off in fault-tolerant circuit design: the joint optimization of code rate (redundancy), minimum distance (fault tolerance), and computational accessibility (shallow-depth implementation of logical gates on encoded data). Building upon von Neumann’s fault-tolerant computing framework, we integrate coding theory with circuit complexity analysis. We establish, for the first time, a rigorous impossibility result: no family of quantum or classical error-correcting codes can simultaneously achieve constant code rate, asymptotically growing minimum distance, and short-depth CNOT-based encoding circuits. This demonstrates an inherent tension—high code rate and large minimum distance necessarily entail exponential or superlinear growth in circuit depth. Our result formally characterizes a fundamental theoretical boundary for fault-tolerant encoding schemes, providing critical guidance for the design of both quantum and classical fault-tolerant architectures.
📝 Abstract
Dating back to the seminal work of von Neumann [von Neumann, Automata Studies, 1956], it is known that error correcting codes can overcome faulty circuit components to enable robust computation. Choosing an appropriate code is non-trivial as it must balance several requirements. Increasing the rate of the code reduces the relative number of redundant bits used in the fault-tolerant circuit, while increasing the distance of the code ensures robustness against faults. If the rate and distance were the only concerns, we could use asymptotically optimal codes as is done in communication settings. However, choosing a code for computation is challenging due to an additional requirement: The code needs to facilitate accessibility of encoded information to enable computation on encoded data. This seems to conflict with having large rate and distance. We prove that this is indeed the case, namely that a code family cannot simultaneously have constant rate, growing distance and short-depth gadgets to perform encoded CNOT gates. As a consequence, achieving good rate and distance may necessarily entail accepting very deep circuits, an undesirable trade-off in certain architectures and applications.