Evaluating Four FPGA-accelerated Space Use Cases based on Neural Network Algorithms for On-board Inference

2026-03-14

AI Summary

This study addresses the critical challenge of limited onboard storage and downlink bandwidth in space missions, where high-fidelity sensor data volumes far exceed transmission capabilities, necessitating efficient on-orbit intelligent processing. For the first time, it systematically evaluates the acceleration performance of neural networks across four representative space applications on an AMD ZCU104 FPGA platform, deploying inference pipelines using both Vitis AI (DPU) and Vitis HLS, with an embedded ARM CPU as the baseline. To handle DPU-unsupported operators such as Sigmoid and 3D convolutions, custom hardware extensions are implemented via HLS. Experimental results demonstrate that Vitis AI achieves up to 34.16× speedup over the CPU, while the HLS-based approach yields a 5.4× improvement. With platform power consumption ranging from 1.5 to 6.75 W, energy per inference is significantly reduced across all scenarios, confirming the efficiency and feasibility of FPGA-based on-orbit intelligent processing.

Technology Category

• Machine Learning: Hardware-aware ML
• Intelligent Robots: Multimodal Perception & Sensor Fusion
• Computer Vision: Remote Sensing / Geospatial AI

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation

Abstract

Space missions increasingly deploy high-fidelity sensors that produce data volumes exceeding onboard buffering and downlink capacity. This work evaluates FPGA acceleration of neural networks (NNs) across four space use cases on the AMD ZCU104 board. We use Vitis AI (AMD DPU) and Vitis HLS to implement inference, quantify throughput and energy, and expose toolchain and architectural constraints relevant to deployment. Vitis AI achieves up to 34.16$\times$ higher inference rate than the embedded ARM CPU baseline, while custom HLS designs reach up to 5.4$\times$ speedup and add support for operators (e.g., sigmoids, 3D layers) absent in the DPU. For these implementations, measured MPSoC inference power spans 1.5-6.75 W, reducing energy per inference versus CPU execution in all use cases. These results show that NN FPGA acceleration can enable onboard filtering, compression, and event detection, easing downlink pressure in future missions.

Problem

• on-board inference
• space missions
• data downlink
• FPGA acceleration
• neural networks

Innovation

• FPGA acceleration
• on-board inference
• neural networks
• Vitis AI
• space missions