HyperCroc: End-to-End Open-Source RISC-V MCU with a Plug-In Interface for Domain-Specific Accelerators

2026-03-12

AI Summary

This work addresses the limited off-chip memory bandwidth and inefficient data transfer capabilities commonly found in open-source microcontrollers, which hinder their support for domain-specific accelerators in machine learning and signal processing. Building upon the open-source RISC-V Croc SoC, this study presents the first integration of a silicon-proven HyperBus controller and a DMA engine, establishing an MCU platform that enables plug-in domain-specific accelerators with low-pin-count, high-bandwidth access to external DRAM/Flash and CPU-intervention-free high-speed data transfers. Leveraging an open-source 130nm PDK and an end-to-end physical implementation flow, the chip can be fully implemented within one hour on a consumer-grade workstation. The first silicon (MLEM) operates reliably at 72 MHz under 1.2 V, validating both the functional completeness of the platform and the robustness of the implementation methodology.

Technology Category

• Machine Learning: Hardware-aware ML
• Application Domains: Internet of Things, Sensor Networks & Smart Cities
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Search and Retrieval-Augmented AI: Vertical and domain-specific search
• Economics, Online Markets and Human Computation: Architectures and workflows that use LLMs for crowd work

Abstract

Domain-Specific architectures with accelerators for machine learning and signal processing require efficient bulk data movement and high-bandwidth access to large datasets. Such capabilities are often absent from minimal open-source microcontrollers (MCUs). We present HyperCroc, an extension to the end-to-end open-source RISC-V Croc system-on-chip (SoC) integrating a silicon-proven HyperBus controller for off-chip DRAM and Flash memory access and a DMA engine, providing a practical MCU-class platform with streamlined plug-in support for domain-specific acceleration. HyperBus offers a low-pin-count PSDRAM interface at up to 400 MB/s, enabling bandwidth-scaled dataset access, while the DMA engine enables autonomous, high-throughput transfers without CPU intervention. HyperCroc preserves Croc's open-source synthesis and physical implementation flow targeting IHP's open 130 nm process design kit (PDK); the full chip can be implemented in under one hour on a consumer-grade workstation. We further report first silicon measurements from MLEM, the first Croc tapeout, confirming that the silicon is fully functional at 72 MHz @ 1.2 V and validating the end-to-end flow.

Problem

• Domain-Specific Architectures
• Microcontrollers
• Data Movement
• Memory Bandwidth
• Accelerators

Innovation

• HyperBus
• DMA engine
• RISC-V MCU
• domain-specific accelerator
• open-source SoC