π€ AI Summary
This study addresses the challenge of achieving high-precision, low-power synchronization in 5G backscatter communication, where conventional methods suffer from excessive resource overhead and poor adaptability. The work proposes a lightweight synchronization mechanism that exploits, for the first time, the mirror symmetry of the envelope of the 5G Primary Synchronization Signal (PSS). By leveraging a symmetry-based differential (SD) detection approach, the method enables efficient PSS acquisition with minimal hardware costβrequiring only 3,175 D flip-flops. This represents a dramatic reduction in resource usage by factors of 87, 181, and 30 compared to NR fine timing, symmetric half-template synchronization, and symmetric autocorrelation synchronization, respectively. The proposed scheme effectively overcomes the resource bottlenecks of existing techniques and is well-suited for multi-template 5G backscatter scenarios.
π Abstract
5G backscatter communication presents an emerging energy-efficient IoT connectivity solution with enhanced availability and data rate advantages over traditional wireless networks. For 5G backscatter, synchronization is crucial as it ensures high-quality transmission. Popular synchronization methods employ autocorrelation and cross-correlation for accurate timing, yet they are constrained by resources. Traditional cross-correlation-based methods for resource utilization optimization also fail in 5G backscatter due to the presence of multiple templates for 5G. A synchronization strategy that supports high accuracy and low power would be highly attractive for wireless backscatter communication. We propose Symmetric Differential (SD)-based Sync, an accurate and resource-efficient synchronization method for 5G backscatter. We have observed that the envelope of the 5G Primary Synchronization Signal (PSS) exhibits a unique mirror symmetry, which enables us to employ differential techniques for low-power PSS detection. We extensively evaluated our design using a testbed of backscatter hardware, SDR gNodeB, and User Equipment (UE). Results show that our SD consumes 3,175 D flip-flops, which is 87x lower than NR fine timing (NFT), 181x lower than symmetry-based semi-template sync (SST), and 30x lower than symmetric autocorrelation (SA)-based sync.