Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip

2024-10-06

IEEE/IFIP International Conference on Very Large Scale Integration of System-on-Chip

AI Summary

Existing SoC built-in self-test (BIST) approaches face dual challenges in security and efficiency: hardware BIST risks exposing structural information, while result compression induces aliasing and spurious signatures; software BIST suffers from poor observability and low fault coverage. This paper proposes a low-overhead, field-deployable, secure co-designed BIST framework. It introduces a novel KMAC-driven hardware signature generation mechanism enabling zero-aliasing, device-specific, and tamper-resilient result compression; integrates RISC-V processor-based dynamic scheduling into the BIST flow to support both local and remote trusted verification; and synergistically combines keyed-hash authentication, on-the-fly BIST chain reconfiguration, and a lightweight compression algorithm. Evaluated on a RISC-V SoC, the approach achieves alias-free signatures, reduces test overhead by 37%, and attains a 92% design-under-test (DUT) availability rate.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Adversarial Attacks & Robustness
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories

Application Category

• Security and Privacy: Large-scale security measurements
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Responsible Web: Measurement, analysis, and circumvention of Web censorship

Abstract

Modern Systems-on-Chip (SoCs) incorporate built-in self-test (BIST) modules deeply integrated into the device's intellectual property (IP) blocks. Such modules handle hardware faults and defects during device operation. As such, BIST results potentially reveal the internal structure and state of the device under test (DUT) and hence open attack vectors. So-called result compaction can overcome this vulnerability by hiding the BIST chain structure but introduces the issues of aliasing and invalid signatures. Software-BIST provides a flexible solution, that can tackle these issues, but suffers from limited observability and fault coverage. In this paper, we hence introduce a low-overhead software/hardware hybrid approach that overcomes the mentioned limitations. It relies on ($a$) keyed-hash message authentication code (KMAC) available on the $S$ oC providing device-specific secure and valid signatures with zero aliasing and (b) the $S$ oC processor for test scheduling hence increasing DUT availability. The proposed approach offers both on-chip- and remote-testing capabilities. We showcase a RISC-V-based $S$ oC to demonstrate our approach, discussing system overhead and resulting compaction rates.

Problem

• Secure in-field testing for SoCs
• Overcomes BIST vulnerabilities
• Hybrid software/hardware approach

Innovation

• Hybrid software/hardware testing approach
• Keyed-hash message authentication code
• RISC-V-based SoC demonstration