GTAC: A Generative Transformer for Approximate Circuits

2025-12-08

arXiv.org

AI Summary

This work proposes GTAC, an end-to-end generative framework for approximate logic synthesis that overcomes the limitations of traditional incremental rewriting strategies, which struggle to efficiently explore the design space under error constraints. GTAC enables scalable approximate circuit design through hierarchical circuit decomposition, Transformer-based subcircuit generation, and candidate selection. It introduces a novel non-redundant encoding scheme and an error-constraint masking mechanism, integrated within a self-evolutionary training strategy, establishing a new paradigm for generative approximate circuit synthesis. Experimental results demonstrate that GTAC reduces delay by 30.9% and gate count by 50.5% compared to exact synthesis baselines, and achieves 6.5% area savings and 4.3× speedup over conventional approximate logic synthesis methods, while reducing sequence length and peak memory consumption by 33.3× and 61.6×, respectively.

Technology Category

• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Machine Learning: Deep Generative Models & Autoencoders
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories

Application Category

• Economics, Online Markets and Human Computation: Economic ramifications for generative AI infrastructure and applications
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs

Abstract

Targeting error-tolerant applications, approximate circuits introduce controlled errors to significantly improve performance, power, and area (PPA) of circuits. In this work, we introduce GTAC, a novel generative Transformer-based model for producing approximate circuits. By leveraging principles of approximate computing and AI-driven EDA, our model innovatively integrates error thresholds into the design process. Experimental results show that compared with a state-of-the-art method, GTAC further reduces 6.4% area under the error rate constraint, while being 4.3x faster.

Problem

• approximate computing
• approximate logic synthesis
• generative AI
• error-tolerant applications
• circuit design

Innovation

• Generative Transformer
• Approximate Logic Synthesis
• Irredundant Encoding
• Error-Tolerant Computing
• Circuit Partitioning