Hardware-Software Co-Design for Event-Driven SNN Deployment on Low-Cost Neuromorphic FPGAs

2026-04-23

AI Summary

This work addresses the challenge of deploying spiking neural networks (SNNs) on low-power FPGAs while preserving consistency between PyTorch-style development and hardware execution. The authors propose a semantics-preserving hardware-software co-design framework that leverages unified metadata artifacts to bridge software specification and board-level implementation. For the first time, this approach enables end-to-end reproducible deployment of PyTorch-defined SNNs onto cost-effective FPGAs with full behavioral equivalence between software and hardware. Implemented with time-to-first-spike (TTFS) encoding, an event-driven architecture, and an 80 MHz routing design, the system achieves 87.40% accuracy on MNIST, with a per-image latency of only 0.1375 µs and dynamic energy consumption of 31.6 nJ. Crucially, it produces results identical to the software reference across all 10,000 test images.

Technology Category

• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web
• Search and Retrieval-Augmented AI: Web query analysis, representation and understanding

Abstract

Low-cost FPGA platforms can broaden access to neuromorphic systems research, but current spiking neural network (SNN) workflows remain divided between hardware-first implementations, which are difficult to integrate with PyTorch-style development, and software-first frameworks, which often stop at simulation or GPU execution. This paper presents a semantics-preserving hardware-software co-design framework for the deterministic deployment of PyTorch-defined SNNs to event-driven FPGA execution. A single exported artifact carries weights, thresholds, connectivity descriptors, and grouped time-to-first-spike (TTFS) decoding metadata from software definition to board execution and is reused unchanged by both the software reference and the board runtime. A 10-class MNIST TTFS classifier implemented in the routed 80 MHz design achieves 87.40\% accuracy and matches the software reference on all 10,000 test images. The programmable-logic path delivers a service latency of 0.1375 μs/image and an estimated dynamic energy of 31.6 nJ/image, while scope-aware comparisons with matched GPU and CPU baselines keep accelerator-only and system-level measurements distinct. These results show that low-cost event-driven FPGA hardware can provide a direct and reproducible software-to-board path for software-defined SNN models.

Problem

• spiking neural network
• hardware-software co-design
• neuromorphic FPGA
• event-driven deployment
• PyTorch integration

Innovation

• hardware-software co-design
• spiking neural networks
• event-driven FPGA
• time-to-first-spike
• deterministic deployment