An Efficient Wireless iBCI Headstage with Adaptive ADC Sample Rate

2026-04-22

AI Summary

This work addresses the limitations of wireless implantable brain–computer interfaces (iBCIs), which are typically constrained by high power consumption and low data throughput. The authors propose a server-driven, adaptive front-end architecture that performs source-level data compression directly at the analog-to-digital converter (ADC) and amplifier stages. By dynamically adjusting the sampling rate per electrode and integrating spike detection, the system circumvents the overhead associated with conventional application-layer compression. Implemented with an electrode-specific sampling strategy on a low-power FPGA, the design achieves a 40 mW reduction in system power consumption and a 3.2× decrease in FPGA resource utilization, while maintaining or even improving decoding accuracy for motor and visual tasks. This approach significantly enhances energy efficiency and hardware utilization without compromising neural signal fidelity.

Technology Category

• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Machine Learning: Hardware-aware ML
• Humans and AI: Brain-Sensing and Analysis

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications
• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

Implantable Brain-Computer Interfaces (iBCIs) are increasingly pivotal in clinical and daily applications. However, wireless iBCIs face severe constraints in power consumption and data throughput. To mitigate these bottlenecks, we propose a wireless iBCI headstage featuring adaptive ADC sampling and spike detection. Distinguishing our design from traditional application-layer compression, we employ a server-driven architecture that achieves source-level efficiency. Specifically, the server learns an optimal, electrode-specific sample rate vector to dynamically reconfigure the ADC hardware. This strategy reduces data volume directly at the acquisition layer (ADC and amplifier) rather than relying on computationally intensive post-digitization processing. Extensive experiments across diverse subjects and arrays demonstrate a power reduction of up to 40 mW and a 3.2$\times$ decrease in FPGA resource utilization, all while maintaining or exceeding decoding accuracy in both motor and visual tasks. This design offers a highly practical solution for long-term in-vivo recording.Our prototype is open-sourced in: https://github.com/liuhongyao99cs/32-Channel-Wireless-BCI-Headstage.

Problem

• wireless iBCI
• power consumption
• data throughput
• implantable Brain-Computer Interface

Innovation

• adaptive ADC sampling
• implantable BCI
• server-driven architecture
• source-level efficiency
• spike detection