Deductive Verification of Weak Memory Programs with View-based Protocols (extended version)

2026-04-22

AI Summary

This work addresses the challenge of verifying correctness in weak-memory concurrent programs, whose behaviors cannot be captured by traditional thread interleaving models, often necessitating cumbersome manual proofs. To overcome this limitation, the paper proposes an automated deductive verification approach that integrates weak-memory separation logic—such as SLR—into the VerCors verifier for the first time. By combining view-based protocols with protocol automata, the method enables efficient reasoning about weak-memory concurrency. The authors extend the VerCors-relaxed framework with enhanced support for atomic operations and refined permission accounting, achieving fully automatic verification of several representative weak-memory programs from the literature. This integration significantly improves both the reliability and degree of automation in verification, with only moderate performance overhead.

Technology Category

• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving
• Machine Learning: Hardware-aware ML

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs

Abstract

Concurrent programming under weak memory concurrency faces substantial challenges to ensure correctness due to program behaviors that cannot be explained by thread interleaving, a.k.a. sequential consistency. While several program logics are proposed to reason about weak memory concurrency, their usage has been limited to intricate manual proofs. On the other hand, the VerCors verifier provides a rich toolset for automated deductive verification for sequential consistency. In this paper, we bridge this gap for automated deductive verification of weak memory concurrent programs with the VerCors deductive verification tool. We propose an approach to encode weak memory concurrency in VerCors. We develop VerCors-relaxed, where we extend the VerCors atomics support and bring concepts from several protocol automata to encode permission-based separation logics for weak memory concurrency models. To demonstrate the effectiveness of our approach, we encode the relaxed fragment of the SLR program logic, a recent state-of-the-art permission-based separation logic for weak memory concurrency in VerCors-relaxed, our extension of VerCors. We use the SLR encoding on VerCors-relaxed to automatically verify several examples from the literature within realistic performance.

Problem

• weak memory concurrency
• deductive verification
• automated verification
• program correctness
• sequential consistency

Innovation

• deductive verification
• weak memory concurrency
• separation logic
• VerCors
• protocol automata