🤖 AI Summary
This work addresses the high computational complexity and latency of traditional implicit neural representations (INRs) in high-resolution scenarios, which stem from per-pixel inference. To overcome this limitation, the authors introduce patch-level inference into the INR framework for the first time, treating non-overlapping image patches as fundamental units and predicting all pixels within a patch in a single forward pass, thereby drastically reducing the number of coordinate queries. A custom FPGA-based hardware accelerator is co-designed, featuring configurable pipelining and support for double-precision computation. With only a 0.6% increase in model parameters, the proposed method achieves a reconstruction quality of 34.97 dB PSNR using 2×2 image patches while reducing inference latency by 75%, substantially improving overall inference efficiency.
📝 Abstract
Implicit Neural Representation (INR) provides an effective approach for continuous signal modeling, but classical per-pixel inference results in quadratic growth in inference count, leading to dramatically increased computational costs in high-resolution application scenarios. To address this issue, we propose a patch-based approach that treats non-overlapping patches as fundamental processing units and predicts entire pixel patches in a single forward pass, significantly reducing the number of inference queries required. To validate the effectiveness of our approach, we propose a hardware acceleration architecture on the Field Programmable Gate Array (FPGA) platform for the INR model, which features a configurable pipeline and supports dual-precision computation. Our patch-based INR achieves comparable reconstruction quality to pixel-level INR (34.97 dB PSNR with 2 x 2 patches) while reducing inference latency by 75% with only 0.6% parameter overhead.