🤖 AI Summary
This work investigates the vulnerability of Apple’s M1 chip to Spectre v1 cross-address-space out-of-place mistraining attacks. To address the lack of architectural documentation, we perform reverse engineering to characterize key parameters of the branch prediction unit (BPU) and its TAGE-based prediction mechanism—marking the first such analysis for M1. We then propose a low-overhead BPU aliasing search technique that overcomes the failure of conventional brute-force approaches on this platform. Experimentally, we demonstrate the first practical cross-address-space Spectre v1 attack on M1, quantitatively bounding the effective search space. Our evaluation further reveals that M1 incorporates partial hardware-level mitigations—offering limited, yet incomplete, protection against such attacks. Collectively, this work uncovers a critical security deficiency in Apple’s custom CPU branch predictor design and establishes an empirical foundation and methodology for architecture-level mitigation assessment.
📝 Abstract
Spectre v1 information disclosure attacks, which exploit CPU conditional branch misprediction, remain unsolved in deployed software. Certain Spectre v1 gadgets can be exploited only by out-of-place mistraining, in which the attacker controls a victim branch's prediction, possibly from another address space, by training a branch that aliases with the victim in the branch predictor unit (BPU) structure. However, constructing a BPU-alias for a victim branch is hard. Consequently, practical out-of-place mistraining attacks use brute-force searches to randomly achieve aliasing. To date, such attacks have been demonstrated only on Intel x86 CPUs. This paper explores the vulnerability of Apple M-Series CPUs to practical out-of-place Spectre v1 mistraining. We show that brute-force out-of-place mistraining fails on the M1. We analytically explain the failure is due to the search space size, assuming (based on Apple patents) that the M1 CPU uses a variant of the TAGE conditional branch predictor. Based on our analysis, we design a new BPU-alias search technique with reduced search space. Our technique requires knowledge of certain M1 BPU parameters and mechanisms, which we reverse engineer. We also use our newfound ability to perform out-of-place Spectre v1 mistraining to test if the M1 CPU implements hardware mitigations against cross-address space out-of-place mistraining -- and find evidence for partial mitigations.