LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models

2025-02-15

AI Summary

Traditional Verilog static checking tools suffer from high false-positive rates and redundant reporting, while commercial EDA tools incur prohibitive licensing costs. To address these limitations, this paper proposes the first LLM-driven static checking framework tailored for hardware design. Our method introduces (1) a novel Logic-Tree Prompting paradigm that explicitly encodes Verilog syntactic structure and semantic logic into hierarchical prompts; (2) a defect propagation tracking module enabling cross-statement error propagation modeling; and (3) the first open-source, mutation-based Verilog bug benchmark suite. Experimental evaluation on the o1-mini model demonstrates that our framework achieves an 18.89% improvement in defect identification accuracy and a 15.56% reduction in false positives compared to the best-performing commercial EDA tool, while consuming less than 10% of its runtime cost.

Technology Category

• Machine Learning: Hardware-aware ML
• Knowledge Representation and Reasoning: Logic Programming
• Natural Language Processing: Fact-Checking / Misinformation Detection (NLP Focus)

Application Category

• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs

Abstract

Code Linting tools are vital for detecting potential defects in Verilog code. However, the limitations of traditional Linting tools are evident in frequent false positives and redundant defect reports. Recent advancements in large language models (LLM) have introduced new possibilities in this area. In this paper, we propose LintLLM, an open-source Linting framework that utilizes LLMs to detect defects in Verilog code via Prompt of Logic-Tree and Defect Tracker. Furthermore, we create an open-source benchmark using the mutation-based defect injection technique to evaluate LLM's ability in detecting Verilog defects. Experimental results show that o1-mini improves the correct rate by 18.89% and reduces the false-positive rate by 15.56% compared with the best-performing EDA tool. Simultaneously, LintLLM operates at less than one-tenth of the cost of commercial EDA tools. This study demonstrates the potential of LLM as an efficient and cost-effective Linting tool for hardware design. The benchmark and experimental results are open-source at URL: https://github.com/fangzhigang32/Static-Verilog-Analysis

Problem

• Detects defects in Verilog code
• Reduces false-positive and redundant reports
• Utilizes LLMs for cost-effective linting

Innovation

• LLM for Verilog Linting
• Prompt of Logic-Tree
• Mutation-based defect injection