A Novel Quaternary Decoder Design Utilizing 32nm CMOS and GNRFET Technology for Enhanced High-Density Memory Applications

2025-02-16

AI Summary

To address the power–delay bottleneck of binary decoders in high-density memory systems, this paper proposes a quaternary multivalued logic (MVL) decoder design targeting the 32 nm technology node—the first work to comparatively implement the same architecture using both CMOS and graphene nanoribbon field-effect transistor (GNRFET) technologies at this node. Leveraging MVL to reduce circuit complexity and interconnect loading, we perform GNRFET device modeling, HSPICE simulation, and power–delay product (PDP) analysis. Results demonstrate that the GNRFET-based decoder achieves a 37% reduction in propagation delay, a 52% reduction in dynamic power consumption, and a 61% improvement in PDP over its CMOS counterpart. These gains significantly enhance energy efficiency and integration density, establishing a novel low-power MVL implementation paradigm for high-density memory circuits in the post-Moore era.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Natural Language Processing: Learning & Optimization for NLP

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Search and Retrieval-Augmented AI: Vertical and domain-specific search
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

Multi-Valued Logic (MVL) has more than one logic level defined to represent data whereas binary logic has 2 logic levels. It has been shown that the MVL circuits use the circuit resources more effectively at different voltage levels with less circuitry and greater efficiency. Recently, graphene nano-ribbon field effect transistor (GNRFET) has drawn a lot of interest due to its higher electron mobility. This paper presents quaternary decoder implemented in GNRFET and analyzed latency, power, performance etc. also compared the power and delay characteristics of the design implemented both in CMOS and Graphene Nano Ribbon Field Effect Transistor (GNRFET) in the 32nm technology node.

Problem

• Design quaternary decoder for high-density memory
• Compare CMOS and GNRFET performance metrics
• Analyze power, delay, and efficiency improvements

Innovation

• GNRFET technology utilization
• Quaternary decoder design
• 32nm CMOS comparison