NoC-Out: A Formally-verified Network-on-Chip Library for Rule-based Hardware Designs

2026-08-25

AI Summary

本文解决了NoC设计缺乏形式化验证的问题，通过开发NoC-Out库生成k维形式化验证的NoC，并扩展Kôika语言支持并发高效设计与模块化推理。

Abstract

The Network-on-Chip (NoC) is the communication backbone of any multiprocessor chip. A failure of the NoC has severe consequences for the whole system. Yet, no approach exists that provides formally-verified NoCs with strong guarantees but without tedious verification effort. Any library that generates formally-verified NoCs needs to be parametric in the structure of the NoC. This requires a hardware description language (HDL) that allows for parametric and concurrent yet efficient hardware designs as well as the necessary program logic to reason about them in a modular fashion. So far, HDLs fall short in both aspects. In this paper, we implement NoC-Out, the first library/generator for formally-verified k-dimensional NoC designs. In order to build NoC-Out, we extended Kôika, a rule-based HDL in the Rocq theorem prover, with support for concurrent yet efficient NoC designs and a program logic for modular, automated reasoning. Given a configuration, NoC-Out produces a k-dimensional torus NoC in Kôika, which can then be compiled to Verilog. Each produced NoC is equipped with a proof that it refines our formal NoC specification; no additional verification effort is required. Our specification proves a strong liveness guarantee, which consequently applies to all generated NoCs. In our evaluation, we find that our verification approach is even required to synthesize efficient NoCs in rule-based HDLs.

Problem

• Network-on-Chip
• formal verification
• hardware description language
• concurrent design
• parametric design

Innovation

• formally-verified NoCs
• rule-based HDL
• concurrent and efficient designs
• modular automated reasoning
• liveness guarantee