EEsizer: LLM-Based AI Agent for Sizing of Analog and Mixed Signal Circuit

2025-09-29

AI Summary

Transistor sizing in analog/mixed-signal (AMS) IC design remains labor-intensive, highly iterative, and knowledge-intensive. Method: This paper introduces EEsizer—the first fully automated, closed-loop transistor sizing agent powered by large language models (LLMs). It tightly integrates an LLM with circuit simulators and custom data analyzers via prompt engineering and chain-of-thought (CoT) reasoning, enabling autonomous optimization without external knowledge bases. Robustness is enhanced via Gaussian perturbation analysis, and cross-process-node transferability is supported. Contribution/Results: Evaluated across six fundamental circuit topologies and eight LLMs, OpenAI o3 was selected as the optimal backbone. On a 20-transistor CMOS op-amp in 90 nm technology, EEsizer successfully completed three distinct sizing tasks—converging to all target specifications within at most 20 iterations.

Technology Category

• Machine Learning: Large Multimodal Models (LMMs)
• Search and Optimization: Sampling/Simulation-based Search
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions
• User Modeling, Personalization and Recommendation: Large Language Models (LLM) for user modeling and recommendation

Abstract

The design of Analog and Mixed-Signal (AMS) integrated circuits (ICs) often involves significant manual effort, especially during the transistor sizing process. While Machine Learning techniques in Electronic Design Automation (EDA) have shown promise in reducing complexity and minimizing human intervention, they still face challenges such as numerous iterations and a lack of knowledge about AMS circuit design. Recently, Large Language Models (LLMs) have demonstrated significant potential across various fields, showing a certain level of knowledge in circuit design and indicating their potential to automate the transistor sizing process. In this work, we propose EEsizer, an LLM-based AI agent that integrates large language models with circuit simulators and custom data analysis functions, enabling fully automated, closed-loop transistor sizing without relying on external knowledge. By employing prompt engineering and Chain-of-Thought reasoning, the agent iteratively explores design directions, evaluates performance, and refines solutions with minimal human intervention. We first benchmarked 8 LLMs on six basic circuits and selected three high-performing models to optimize a 20-transistor CMOS operational amplifier, targeting multiple performance metrics, including rail-to-rail operation from 180 nm to 90 nm technology nodes. Notably, OpenAI o3 successfully achieved the user-intended target at 90 nm across three different test groups, with a maximum of 20 iterations, demonstrating adaptability and robustness at advanced nodes. To assess design robustness, we manually designed a bias circuit and performed a variation analysis using Gaussian-distributed variations on transistor dimensions and threshold voltages.

Problem

• Automating transistor sizing for analog and mixed-signal circuits
• Reducing manual effort in integrated circuit design iterations
• Integrating LLMs with circuit simulators for closed-loop optimization

Innovation

• LLM-based AI agent automates transistor sizing process
• Integrates language models with circuit simulators and analysis
• Uses prompt engineering and Chain-of-Thought reasoning iterations