Uncertainty-triggered wake-up enables energy-efficient, error-resilient edge AI with memristor front ends

2026-05-28

AI Summary

This work addresses the reliability challenges in memristor-based edge AI systems arising from device variability and environmental sensitivity by proposing a heterogeneous inference architecture. The approach employs a low-power memristor-based Bayesian machine as a front-end probabilistic screener, which triggers a high-precision CPU back-end for final decision-making only when output uncertainty exceeds a threshold. This uncertainty-driven wake-up mechanism effectively converts unreliable front-end outputs into recoverable events, thereby preventing silent errors. The system integrates experimentally characterized memristor arrays, an FPGA-implemented wake-up circuit, and a programmable CPU, complemented by post-layout ASIC analysis. Evaluated on an ECG heartbeat classification task, the framework maintains high accuracy even under front-end degradation due to voltage or programming margin variations, with overall energy efficiency governed primarily by wake-up frequency—offering practical design guidelines for front-end operating point selection.

Abstract

Memristor computing offers a route to low-energy edge AI, but device variability, sensitivity to operating conditions, and system-integration challenges can hinder deployment. Here we show that these limitations can be mitigated by using memristor AI not as the final decision maker but as the ultra-low-power, always-on front end of a heterogeneous inference system. We implement this architecture by coupling a fabricated memristor Bayesian machine to a programmable CPU running a higher-power, higher-accuracy software neural network. The memristor front end acts as a probabilistic screener. When it predicts an abnormal event or produces an ambiguous or invalid output, a dedicated hardware wake-up path activates the CPU, which produces the final decision. We validate this architecture on a heartbeat-classification benchmark by interfacing the fabricated Bayesian machine with an FPGA-based wake-up platform and CPU back end. The resulting uncertainty-triggered wake-up system achieves high final classification accuracy under nominal operation and maintains this accuracy even when the memristor front end is degraded by voltage scaling or reduced programming margins, because unreliable outputs are converted into recoverable wake-up events instead of becoming silent errors. Post-layout analysis of an ASIC implementation shows that average energy is governed primarily by wake-up frequency, providing practical design rules for choosing front-end operating points. These results establish uncertainty-triggered wake-up as a strategy for energy-efficient, error-resilient edge AI.

Problem

• memristor
• edge AI
• device variability
• error resilience
• energy efficiency

Innovation

• uncertainty-triggered wake-up
• memristor computing
• edge AI
• error-resilient inference
• heterogeneous architecture