High-Performance Low-Power Adiabatic Systolic Array Design in Advanced FinFET Nodes

2026-08-30

AI Summary

研究针对低功耗需求，通过在16nm FinFET技术中实现带共振4相电源时钟的adiabatic逻辑MAC阵列设计方法，于GHz时钟下降低了高达42%的核心能耗。

Abstract

Adiabatic logic has traditionally been recognized as a low-power solution but constrained to low clock speeds to preserve adiabatic behavior. For advanced FinFET nodes, however, clock frequencies have plateaued due to power/thermal concerns (dark silicon) even as the intrinsic device speeds have continued to scale. This convergence opens an opportunity for adiabatic logic to maintain adiabatic behavior even at GHz clocks. We demonstrate an adiabatic logic (AL) design methodology through a MAC systolic array implemented in commercial 16 nm FinFET technology with a resonant 4-phase power clock (PCK) generator, including digital-to-AL and AL-to-digital interfaces. Simulations show that the AL MAC systolic array at 1 GHz achieves power reductions of up to 42% and 36% at the core and system levels, respectively, compared to digital counterparts. Scaling to more advanced nodes should provide even better power/performance metrics.

Problem

• adiabatic logic
• low-power
• GHz clocks
• FinFET nodes
• systolic array

Innovation

• Adiabatic Logic
• FinFET Nodes
• 4-Phase Power Clock Generator
• Power Reduction