Enhanced Hybrid Temporal Computing Using Deterministic Summations for Ultra-Low-Power Accelerators

2025-09-26

AI Summary

Existing Hybrid Temporal Computing (HTC) architectures suffer from accuracy degradation due to MUX-based scaled addition. To address this, this paper proposes a precision-enhanced hybrid temporal computing framework. Its core innovations are the Exact Multi-Input Binary Accumulator (EMBA) and the Threshold-based Deterministic Scaling Adder (DTSA), enabling lossless, deterministic addition while supporting both unipolar and bipolar pulse rate–time joint encoding. A fabricated 4×4 multiply-accumulate (MAC) unit is evaluated on FIR filtering and 8-point DCT/iDCT. In unipolar mode, it achieves RMSE comparable to CBSC, with 94% higher accuracy than MUX-HTC, alongside 23% lower power consumption and 7% smaller area. In bipolar mode, it attains an RMSE of 2.09%, representing an 83% accuracy improvement over prior HTC approaches, while significantly outperforming state-of-the-art designs in energy efficiency and area.

Technology Category

• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Temporal Planning
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding

Application Category

• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Graph Algorithms and Modeling for the Web: Algorithms and analysis for heterogeneous, signed, attributed, multi-relational, temporal, higher-order, and annotated Web-related graphs
• Security and Privacy: Privacy-enhancing technologies

Abstract

This paper presents an accuracy-enhanced Hybrid Temporal Computing (E-HTC) framework for ultra-low-power hardware accelerators with deterministic additions. Inspired by the recently proposed HTC architecture, which leverages pulse-rate and temporal data encoding to reduce switching activity and energy consumption but loses accuracy due to its multiplexer (MUX)-based scaled addition, we propose two bitstream addition schemes: (1) an Exact Multiple-input Binary Accumulator (EMBA), which performs precise binary accumulation, and (2) a Deterministic Threshold-based Scaled Adder (DTSA), which employs threshold logic for scaled addition. These adders are integrated into a multiplier accumulator (MAC) unit supporting both unipolar and bipolar encodings. To validate the framework, we implement two accelerators: a Finite Impulse Response (FIR) filter and an 8-point Discrete Cosine Transform (DCT)/iDCT engine. Results on a 4x4 MAC show that, in unipolar mode, E-HTC matches the RMSE of state-of-the-art Counter-Based Stochastic Computing (CBSC) MAC, improves accuracy by 94% over MUX-based HTC, and reduces power and area by 23% and 7% compared to MUX-based HTC and 64% and 74% compared to CBSC. In bipolar mode, E-HTC MAC achieves 2.09% RMSE -- an 83% improvement over MUX-based HTC -- and approaches CBSC's 1.40% RMSE with area and power savings of 28% and 43% vs. MUX-based HTC and about 76% vs. CBSC. In FIR experiments, both E-HTC variants yield PSNR gains of 3--5 dB (30--45% RMSE reduction) while saving 13% power and 3% area. For DCT/iDCT, E-HTC boosts PSNR by 10--13 dB (70--75% RMSE reduction) while saving area and power over both MUX- and CBSC-based designs.

Problem

• Improving accuracy of hybrid temporal computing for ultra-low-power accelerators
• Replacing inaccurate MUX-based additions with deterministic summation schemes
• Achieving higher precision while maintaining low power and area efficiency

Innovation

• Exact Multiple-input Binary Accumulator for precise accumulation
• Deterministic Threshold-based Scaled Adder using threshold logic
• Enhanced Hybrid Temporal Computing framework with deterministic additions