FedBit: Accelerating Privacy-Preserving Federated Learning via Bit-Interleaved Packing and Cross-Layer Co-Design

2025-09-26

AI Summary

To address the high computational overhead and ciphertext expansion caused by fully homomorphic encryption (FHE) in federated learning, this paper proposes FedBit, a software–hardware co-optimization framework. Methodologically, FedBit introduces (i) bit-interleaved packing—a novel technique that embeds multiple model parameters into individual coefficients of BFV ciphertexts, overcoming conventional word-level packing constraints—and (ii) an FPGA-specific FHE accelerator with a memory-aware dataflow, enabling fine-grained parallelism and efficient hardware resource utilization. Experimental results demonstrate that FedBit achieves a 100× speedup in encryption throughput and reduces communication overhead by 60.7% compared to baseline FHE-based federated learning systems, while preserving model accuracy. To the best of our knowledge, FedBit is the first end-to-end system for privacy-preserving federated learning that jointly supports bit-level ciphertext compression and hardware-native acceleration.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Learning to Search
• Computer Vision: Learning & Optimization for CV

Application Category

• User Modeling, Personalization and Recommendation: Federated recommendation systems and personalization
• Systems and Infrastructure for Web, Mobile and WoT: Federated Web and WoT systems, including distributed, federated and edge-based data processing
• Security and Privacy: Privacy-enhancing technologies

Abstract

Federated learning (FL) with fully homomorphic encryption (FHE) effectively safeguards data privacy during model aggregation by encrypting local model updates before transmission, mitigating threats from untrusted servers or eavesdroppers in transmission. However, the computational burden and ciphertext expansion associated with homomorphic encryption can significantly increase resource and communication overhead. To address these challenges, we propose FedBit, a hardware/software co-designed framework optimized for the Brakerski-Fan-Vercauteren (BFV) scheme. FedBit employs bit-interleaved data packing to embed multiple model parameters into a single ciphertext coefficient, thereby minimizing ciphertext expansion and maximizing computational parallelism. Additionally, we integrate a dedicated FPGA accelerator to handle cryptographic operations and an optimized dataflow to reduce the memory overhead. Experimental results demonstrate that FedBit achieves a speedup of two orders of magnitude in encryption and lowers average communication overhead by 60.7%, while maintaining high accuracy.

Problem

• Accelerating privacy-preserving federated learning with reduced computational overhead
• Minimizing ciphertext expansion in homomorphic encryption for federated learning
• Reducing communication overhead while maintaining model accuracy in FL

Innovation

• Bit-interleaved packing minimizes ciphertext expansion
• FPGA accelerator handles cryptographic operations efficiently
• Cross-layer co-design reduces memory and communication overhead