Learning-Augmented Performance Model for Tensor Product Factorization in High-Order FEM

2026-01-11

arXiv.org

AI Summary

This work addresses the limitations of traditional memory-bandwidth-based performance models—such as Roofline and ECM—in accurately predicting the performance of tensor n-mode product kernels under high arithmetic intensity, particularly on processors with high SIMD instruction latency like the Fujitsu A64FX. To overcome this challenge, the authors propose a learning-augmented performance model that integrates dependency chain analysis with XGBoost regression, introducing instruction-level dependency features for the first time into performance prediction for high-order finite element computations. The approach effectively evaluates the execution efficiency of various loop tiling strategies, achieving mean absolute percentage errors of only 1%–24% on both the A64FX and Intel Xeon Gold 6230 platforms, substantially outperforming the Roofline (42%–256%) and ECM (5%–117%) models.

Technology Category

• Machine Learning: Matrix & Tensor Methods
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures
• Knowledge Representation and Reasoning: Computational Complexity of Reasoning

Application Category

• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems

Abstract

Accurate performance prediction is essential for optimizing scientific applications on modern high-performance computing (HPC) architectures. Widely used performance models primarily focus on cache and memory bandwidth, which is suitable for many memory-bound workloads. However, it is unsuitable for highly arithmetic intensive cases such as the sum-factorization with tensor $n$-mode product kernels, which are an optimization technique for high-order finite element methods (FEM). On processors with relatively high single instruction multiple data (SIMD) instruction latency, such as the Fujitsu A64FX, the performance of these kernels is strongly influenced by loop-body splitting strategies. Memory-bandwidth-oriented models are therefore not appropriate for evaluating these splitting configurations, and a model that directly reflects instruction-level efficiency is required. To address this need, we develop a dependency-chain-based analytical formulation that links loop-splitting configurations to instruction dependencies in the tensor $n$-mode product kernel. We further use XGBoost to estimate key parameters in the analytical model that are difficult to model explicitly. Evaluations show that the learning-augmented model outperforms the widely used standard Roofline and Execution-Cache-Memory (ECM) models. On the Fujitsu A64FX processor, the learning-augmented model achieves mean absolute percentage errors (MAPE) between 1% and 24% for polynomial orders ($P$) from 1 to 15. In comparison, the standard Roofline and ECM models yield errors of 42%-256% and 5%-117%, respectively. On the Intel Xeon Gold 6230 processor, the learning-augmented model achieves MAPE values from 1% to 13% for $P$=1 to $P$=14, and 24% at $P$=15. In contrast, the standard Roofline and ECM models produce errors of 1%-73% and 8%-112% for $P$=1 to $P$=15, respectively.

Problem

• performance modeling
• tensor product factorization
• high-order FEM
• instruction-level efficiency
• loop splitting

Innovation

• learning-augmented modeling
• tensor n-mode product
• instruction-level performance modeling
• loop splitting
• high-order FEM