🤖 AI Summary
This work addresses the manufacturing complexity of beyond-diagonal reconfigurable intelligent surfaces (BD-RISs) arising from dense inter-element interconnections, which typically necessitate multilayer printed circuit boards (PCBs). To tackle this challenge, the authors introduce, for the first time, a graph-theoretic modeling approach that abstracts the BD-RIS connectivity structure as a graph. Leveraging planarity testing theory, they systematically identify planar connection architectures realizable on double-layer PCBs. Within this constraint, they further pinpoint the BD-RIS topology that maximizes degrees of freedom, achieving excellent beamforming performance while substantially reducing hardware implementation complexity. This study thus provides both theoretical grounding and a practical design pathway toward low-cost, high-performance RIS implementations.
📝 Abstract
Reconfigurable intelligent surfaces (RISs) enable programmable control of the wireless propagation environment and are key enablers for future networks. Beyond-diagonal RIS (BD-RIS) architectures enhance conventional RIS by interconnecting elements through tunable impedance components, offering greater flexibility with higher circuit complexity. However, excessive interconnections between BD-RIS elements require multi-layer printed circuit board (PCB) designs, increasing fabrication difficulty. In this letter, we use graph theory to characterize the BD-RIS architectures that can be realized on double-layer PCBs, denoted as planar-connected RISs. Among the possible planar-connected RISs, we identify the ones with the most degrees of freedom, expected to achieve the best performance under practical constraints.