Photonics-Aware Planning-Guided Automated Electrical Routing for Large-Scale Active Photonic Integrated Circuits

2025-09-28

AI Summary

Large-scale active photonic integrated circuits (PICs) lack end-to-end automated routing solutions for co-designing photonic waveguides and metal interconnects. Method: This paper introduces the first fully automated, unified routing framework for photonic–electronic heterogeneous interconnects. It features a physics-aware global router and a sequence-consistent track assignment mechanism that jointly optimizes waveguide congestion and crossovers, incorporates device-layout awareness, and enables soft-guided detailed routing—implemented via customized heuristics and efficient graph-search algorithms. Results: Experiments on multiple large-scale photonic chips demonstrate that our framework reduces vias by 99%, decreases design rule checking (DRC) violations by 98%, and accelerates runtime by 17× compared to manual and conventional VLSI-based routing approaches. It significantly improves routing completion rate and DRC compliance while enabling scalable, robust photonic–electronic co-routing.

Technology Category

• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Search and Optimization: Mixed Discrete/Continuous Search

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web
• Security and Privacy: Large-scale security measurements

Abstract

The rising demand for AI training and inference, as well as scientific computing, combined with stringent latency and energy budgets, is driving the adoption of integrated photonics for computing, sensing, and communications. As active photonic integrated circuits (PICs) scale in device count and functional heterogeneity, physical implementation by manual scripting and ad-hoc edits is no longer tenable. This creates an immediate need for an electronic-photonic design automation (EPDA) stack in which physical design automation is a core capability. However, there is currently no end-to-end fully automated routing flow that coordinates photonic waveguides and on-chip metal interconnect. Critically, available digital VLSI and analog/custom routers are not directly applicable to PIC metal routing due to a lack of customization to handle constraints induced by photonic devices and waveguides. We present, to our knowledge, the first end-to-end routing framework for large-scale active PICs that jointly addresses waveguides and metal wires within a unified flow. We introduce a physically-aware global planner that generates congestion- and crossing-aware routing guides while explicitly accounting for the placement of photonic components and waveguides. We further propose a sequence-consistent track assignment and a soft guidance-assisted detailed routing to speed up the routing process with significantly optimized routability and via usage. Evaluated on various large PIC designs, our router delivers fast, high-quality active PIC routing solutions with fewer vias, lower congestion, and competitive runtime relative to manual and existing VLSI router baselines; on average it reduce via count by ~99%, user-specified design rule violation by ~98%, and runtime by 17x, establishing a practical foundation for EPDA at system scale.

Problem

• Automating electrical routing for large-scale photonic integrated circuits
• Coordinating photonic waveguides with on-chip metal interconnect
• Overcoming limitations of existing VLSI routers for photonic constraints

Innovation

• End-to-end routing framework for photonic integrated circuits
• Physically-aware global planner for congestion optimization
• Sequence-consistent track assignment with soft guidance