C2C-Explorer: An Exploration Framework for Chip-to-Chip Interconnect Architectures in LLM Cloud Computing Systems

2026-08-09

AI Summary

This work addresses three key challenges in interconnect design for large language model (LLM) inference: realistic traffic generation, large-scale cycle-accurate simulation, and exploration of a vast design space. The authors propose the first end-to-end co-optimization framework, integrating an LLM workload-driven traffic generator, a scalable interconnect simulator supporting switch- and fully-connected topologies (up to 512 chips), and a Bayesian optimization-based metric-guided exploration mechanism. A novel hybrid cycle- and event-driven simulation model is introduced to enhance efficiency. Evaluated on a 32-XPU system running DeepSeek-R1-671B, the approach identifies an interconnect configuration that improves throughput by 44.1% and reduces memory footprint by 98.4%, while achieving up to 7.8× faster simulation than a purely cycle-accurate baseline with timing errors of only 2.46–8.23%.

Abstract

The scaling-up of large language models (LLMs) necessitates computing systems to have multi-processor-chip architectures, elevating the importance of chip-to-chip (C2C) communication. However, designing efficient C2C hardware architectures for LLM workloads faces three key challenges: generating realistic LLM-specific C2C traffic, accurately simulating hardware-level communication at scale, and efficiently exploring the exponentially large C2C design space. We propose C2C-Explorer, an adaptive Bayesian DSE framework that integrates a LLM-workload-driven traffic generator, a scalable interconnect simulator (switch/full-mesh, up to 512 chips), and a metric-guided evaluator into a workload-to-hardware optimization pipeline, enabling systematic C2C architectural co-design under realistic LLM workloads. Validated against FPGA-based C2C prototypes, the C2C simulator achieves 2.46-8.23% end-to-end timing error across diverse traffic patterns. Its hybrid cycle and event model further accelerates large-scale simulation by up to 7.8$\times$ over a pure cycle-accurate baseline. Applied to a 32-XPU DeepSeek-R1-671B inference workload, C2C-Explorer identifies configurations that improve goodput by 44.1% and reduce memory by 98.4%. C2C-Explorer is open-source and available at https://github.com/Selinaee/C2C-Explorer.

Problem

• chip-to-chip interconnect
• large language models
• design space exploration
• hardware architecture
• communication simulation

Innovation

• Chip-to-Chip Interconnect
• Design Space Exploration
• LLM Workload Modeling
• Scalable Interconnect Simulation
• Bayesian Optimization