CryptRISC: A Secure RISC-V Processor for High-Performance Cryptography with Power Side-Channel Protection

2026-02-23

AI Summary

This work addresses the vulnerability of cryptographic computations to power side-channel attacks by proposing an instruction set-driven dynamic operand masking mechanism integrated into the RISC-V CVA6 core. Unlike existing software-based masking schemes with high overhead or rigid hardware solutions lacking flexibility, the proposed approach enables transparent, algorithm-adaptive protection within the execution pipeline. It uniquely supports runtime switching among Boolean, affine, and arithmetic masking based on instruction semantics and algebraic domains—without modifying instruction encoding. By extending the 64-bit scalar cryptographic instruction set and incorporating a domain detection layer alongside a mask control unit, the design achieves field-aware operand randomization. Evaluated on AES, SHA-256/512, SM3, and SM4, the implementation yields up to 6.80× speedup over pure software masking while incurring only 1.86% additional hardware overhead.

Technology Category

• Computer Vision: Adversarial Attacks & Robustness
• Machine Learning: Hardware-aware ML
• Application Domains: Security

Application Category

• Security and Privacy: Applications of cryptography
• Responsible Web: Measurement, analysis, and circumvention of Web censorship
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems

Abstract

Cryptographic computations are fundamental to modern computing, ensuring data confidentiality and integrity. However, these operations are highly vulnerable to power side-channel attacks that exploit variations in power consumption to leak sensitive information. Masking is a widely used countermeasure, yet software-based techniques often introduce significant performance overhead and implementation complexity, while fixed-function hardware masking lacks flexibility across diverse cryptographic algorithms. In this paper, we present CryptRISC, the first RISC-V-based processor that combines cryptographic acceleration with hardware-level power side-channel resistance through an ISA-driven operand masking framework. Our design extends the CVA6 core with 64-bit RISC-V Scalar Cryptography Extensions and introduces two microarchitectural components: a Field Detection Layer, which identifies the dominant algebraic field of each cryptographic instruction, and a Masking Control Unit, which applies field-aware operand randomization at runtime. This enables dynamic selection of Boolean, affine, or arithmetic masking schemes based on instruction semantics, providing optimized protection across algorithms including AES, SHA-256, SHA-512, SM3, and SM4. Unlike prior approaches relying on static masking logic or software instrumentation, our method performs operand masking transparently within the execution pipeline without modifying instruction encoding. Experimental results show speedups up to 6.80$\times$ over baseline software implementations, with only a 1.86% hardware overhead relative to the baseline CVA6 core, confirming the efficiency and practicality of CryptRISC.

Problem

• power side-channel attacks
• masking
• cryptographic acceleration
• RISC-V
• hardware security

Innovation

• RISC-V
• power side-channel protection
• operand masking
• cryptographic acceleration
• hardware security