First Demonstration of 28 nm Fabricated FeFET-Based Nonvolatile 6T SRAM

2026-03-27

AI Summary

This work addresses the high standby power consumption of edge computing devices caused by the volatility of conventional 6T SRAM. To overcome this limitation, the authors propose a hybrid non-volatile 6T SRAM architecture based on p-type ferroelectric field-effect transistors (p-FeFETs), wherein only the two PMOS pull-up transistors are replaced with p-FeFETs. This design achieves zero standby power and rapid power-off recovery without increasing transistor count. Notably, it represents the first manufacturable FeFET-integrated SRAM cell fabricated in a commercial 28 nm process, occupying an area of 99 μm² and exhibiting read latency comparable to conventional SRAM. Both SPICE simulations and silicon measurements confirm its high-speed operation, low power consumption, and reliable state restoration, demonstrating strong suitability for IoT and edge AI applications.

Abstract

With the staggering increase of edge compute applications like Internet-of-Things (IoT) and artificial intelligence (AI), the demand for fast, energy-efficient on-chip memory is growing. While the fast and mature static random-access memory (SRAM) technology is the standard choice, its volatility requires a constant supply voltage to operate and store data. Especially in edge AI and IoT devices that often idle, the leakage power consumes a significant portion of the constrained power budget. For this, emerging non-volatile memory (NVM) technologies such as Resistive RAM and ferroelectric FET (FeFET) offer zero-standby power consumption but suffer from integration and performance tradeoffs. To harness the benefits of the different technologies, hybrid architectures have been proposed, combining SRAM with NVM devices. This work proposes a hybrid non-volatile SRAM (nvSRAM) architecture based on recently demonstrated PMOS FeFETs (p-FeFETs). By replacing the two PMOS pull-up transistors with p-FeFETs, we achieve non-volatility without additional transistors. The design supports seamless power-down and restore operation, thus eliminating standby leakage. SPICE simulations in a commercial 28 nm technology show read latency comparable to conventional SRAM, and on-silicon measurements show robust restore behavior. With this, we are the first to demonstrate a fabricated 6T nvSRAM cell design. The resulting cell achieves an area footprint of 99 $μm^2$. The read path remains identical to baseline SRAM, enabling high-speed operation while being non-volatile, making it ideal for IoT and edge systems.

Problem

• non-volatile memory
• SRAM
• standby power
• edge computing
• FeFET

Innovation

• FeFET
• non-volatile SRAM
• 6T nvSRAM
• 28 nm fabrication
• zero standby power