Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System

2026-03-26

AI Summary

This work addresses the performance unpredictability in real-time systems caused by bank-level interference in shared DRAM on multi-core SoCs. To mitigate this issue, the authors propose a fine-grained bandwidth regulation mechanism that exploits DRAM bank-level parallelism to enforce per-bank bandwidth isolation. Implemented on an open-source RISC-V SoC, this approach refines the regulation granularity from the core level down to individual DRAM banks for the first time. By leveraging the generational stability of modern DRAM bandwidth guarantees, the mechanism effectively defends against single-bank attacks. Evaluation using the FireSim simulation platform demonstrates that the proposed method not only preserves performance isolation for real-time tasks but also improves the average throughput of best-effort workloads by 5.74×.

Abstract

Modern multicore system-on-chips (SoCs) share off-chip DRAM across cores, where bank-level interference can significantly degrade performance and threaten real-time guarantees. While prior work has focused on per-core bandwidth regulation, these approaches treat main memory as a monolithic resource and overlook DRAM's inherent bank-level parallelism. We show that DRAM interference is fundamentally a bank-level phenomenon. We characterize the guaranteed bandwidth of modern DRAM, demonstrate that it remains effectively constant across generations, and show how this limitation can be exploited by single-bank attacks. These results highlight the need for bank-aware memory management for predictable and efficient real-time systems. We design and implement a novel per-bank memory bandwidth regulator in an open-source RISC-V SoC and evaluate it using FireSim with both synthetic and real-world workloads. Our evaluation demonstrates that per-bank regulation effectively mitigates adversarial bank contention and achieves a 5.74x average throughput improvement for best-effort workloads over traditional bank-oblivious approaches while providing the same-level of performance isolation guarantees for real-time workloads.

Problem

• DRAM interference
• bank-level contention
• real-time systems
• memory bandwidth regulation
• performance isolation

Innovation

• per-bank bandwidth regulation
• DRAM bank-level interference
• real-time systems
• memory isolation
• RISC-V SoC