FireBridge: Cycle-Accurate Hardware + Firmware Co-Verification for Modern Accelerators

2026-03-26

AI Summary

This work addresses the inefficiencies in hardware-software co-integration of modern accelerators, which stem from architectural complexity, deep memory hierarchies, and heavy reliance on production firmware. Traditional FPGA-based simulation workflows suffer from slow debugging cycles and prolonged iteration times. To overcome these limitations, we present the first framework enabling cycle-accurate co-verification of production firmware with RTL or gate-level hardware models within standard simulators such as VCS, Xcelium, and Vivado Xsim. By compiling firmware to x86 and bridging it with the hardware emulation subsystem—augmented with a randomized memory bridge—the framework supports second-scale debugging, register-level protocol validation, off-chip dataflow analysis, and memory congestion emulation. Evaluated on accelerators including systolic arrays and CGRAs, our approach achieves up to 50× faster debugging and significantly enhances parallel development efficiency and functional verification reliability for heterogeneous computing platforms.

Abstract

Hardware-firmware integration is becoming a productivity bottleneck due to the increasing complexity of accelerators, characterized by intricate memory hierarchies and firmware-intensive execution. While numerous verification techniques focus on early-stage, approximate modeling of such systems to speed up initial development, developers still rely heavily on FPGA emulation to integrate firmware with RTL/HLS hardware, resulting in significant delays in debug iterations and time-to-market. We present a fast, cycle-accurate co-verification framework that bridges production firmware and RTL/gate-level hardware. FIREBRIDGE enables firmware debugging, profiling, and verification in seconds using standard simulators such as VCS, Vivado Xsim, or Xcelium, by compiling the firmware for x86 and bridging it with simulated subsystems via randomized memory bridges. Our approach provides off-chip data movement profiling, memory congestion emulation, and register-level protocol testing, which are critical for modern accelerator verification. We demonstrate a speedup of up to 50x in debug iteration over the conventional FPGA-based flow for system integration between RTL/HLS and production firmware on various types of accelerators, such as systolic arrays and CGRAs, while ensuring functional equivalence. FIREBRIDGE accelerates system integration by supporting robust co-verification of hardware and firmware, and promotes a structured, parallel development workflow tailored for teams building heterogeneous computing platforms.

Problem

• hardware-firmware co-verification
• accelerator integration
• cycle-accurate simulation
• debug iteration
• FPGA emulation

Innovation

• cycle-accurate co-verification
• firmware-hardware integration
• randomized memory bridges
• accelerator verification
• x86-RTL co-simulation